Senior PD Engineer

Microsoft's Silicon, Cloud Hardware, and Infrastructure Engineering team powers Microsoft's cloud infrastructure and 200+ online businesses.
Embedded
Principal Software Engineer
Hybrid
5,000+ Employees
10+ years of experience
Enterprise SaaS · Cloud

Description For Senior PD Engineer

Microsoft's Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team is at the forefront of developing cutting-edge silicon solutions for Microsoft's expanding cloud infrastructure. As part of the Cloud Compute Development Organization (CCDO), we're seeking a Senior Physical Design Engineer to join our silicon hardware physical design team. This role focuses on RTL to GDS methodology, design convergence, and quality assurance for CPU-based custom SOC designs.

The position offers an opportunity to work on groundbreaking projects developing CPU-based SOCs for data centers, directly impacting Microsoft's cloud computing capabilities. You'll be responsible for implementing designs through synthesis, floorplanning, place and route, while ensuring optimal timing and physical verification.

The ideal candidate brings 10+ years of semiconductor design experience, with deep expertise in physical design implementation and optimization. You'll work with state-of-the-art EDA tools and be responsible for critical aspects of chip design, from power analysis to clock distribution.

This role offers the chance to work with Microsoft's diverse portfolio of products including Azure, Office 365, Xbox Live, and Teams. You'll collaborate with talented engineers across multiple disciplines, contribute to innovative solutions, and help shape the future of Microsoft's cloud infrastructure.

Benefits include industry-leading healthcare, educational resources, parental leave, and opportunities for professional growth. The position offers a hybrid work arrangement with up to 50% work from home flexibility, based in Hyderabad, India.

Last updated 24 days ago

Responsibilities For Senior PD Engineer

  • Own execution from synthesis to place and route of partitions through all signoff
  • Own partition floorplanning for optimizing blocks for Power, Performance and Area
  • Converge design through all signoff aspects
  • Partner with PD flow/CAD team and PD methodology team
  • Collaborate with RTL team to resolve design issues
  • Implement robust clock distribution solutions
  • Make technical trade-offs between power, area, and timing (PPA)
  • Mentor junior engineers on technical issues

Requirements For Senior PD Engineer

Python
  • BS/BE/BTech/MS/ME/MTech in Electronics or Microelectronics/VLSI, or Electrical Engineering
  • 10+ years of experience in semiconductor design
  • Experience with EDA tools like Fusion Compiler, Primetime, StarRC, RedHawk, Formality
  • Strong understanding of constraints generation, STA, timing optimization, and timing closure
  • Experience in power analysis and low power optimization methodology
  • Automation skills using scripting languages such as Perl, TCL, or Python
  • Great communication, collaboration and teamwork skills

Benefits For Senior PD Engineer

Medical Insurance
Education Budget
Parental Leave
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

Interested in this job?

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