Senior Silicon Engineering

Microsoft is a global technology company that empowers every person and every organization on the planet to achieve more.
$117,200 - $229,200
Backend
Senior Software Engineer
Hybrid
5,000+ Employees
7+ years of experience
Enterprise SaaS

Description For Senior Silicon Engineering

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

The Data Processing Unit (DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer to join their front-end silicon team. You will be responsible for delivering cutting-edge, high performance, low power, scalable and programmable DPU silicon.

As a Senior Silicon Engineer, you will:

  • Validate silicon to solve complex problems in a datacenter
  • Lead key components of functional validation of complex ASIC SOC using UVM/C test bench
  • Perform Pre-Silicon SoC verification and Post-Silicon/FPGA validation
  • Work with cross-functional teams and influence next generation designs
  • Develop test plans, C tests, and infrastructure for functional validation
  • Run tests, debug failures, and create stress and performance scenarios
  • Participate in chip bring up and write test firmware
  • Innovate to improve validation efficiency
  • Coach and mentor others in your areas of expertise

Required Qualifications:

  • 7+ years of related technical engineering experience or equivalent combination of education and experience
  • 5+ years of experience in RTL Verification using UVM/C verification methodology
  • 5+ years of experience in Ethernet, TCP/IP, MAC/PCS, Networking blocks
  • 5+ years of experience in verification and development of complex System on Chips
  • In-depth understanding of processors and peripheral interconnect bus protocols and architectures
  • Knowledge of Verilog, System Verilog, UVM methodology

The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year, with a higher range applicable to specific work locations in the San Francisco Bay area and New York City metropolitan area.

Microsoft offers a comprehensive benefits package including industry-leading healthcare, educational resources, savings and investments, parental leave, and generous time off. Join us in our mission to empower every person and every organization on the planet to achieve more.

Last updated 3 months ago

Responsibilities For Senior Silicon Engineering

  • Validating silicon to solve complex problems in a datacenter
  • Lead key components of functional validation of complex ASIC SOC using UVM/C test bench
  • Perform Pre-Silicon SoC verification, Post-Silicon/FPGA validation by defining testing strategies
  • Work with Cross-functional teams for project execution and influence next generation designs
  • Develop Test plan, C tests and infrastructure to complete functional validation
  • Running tests, debugging failures, creating stress and performance scenarios
  • Actively participate in chip bring up and write test firmware
  • Innovate to improve validation efficiency through methodologies and tools
  • Coach and mentor others in your areas of expertise

Requirements For Senior Silicon Engineering

  • 7+ years of related technical engineering experience
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
  • 5+ years of experience in RTL Verification using UVM/C verification methodology
  • 5+ years of experience in Ethernet, TCP/IP, MAC/PCS, Networking blocks
  • 5+ years of experience in verification and development of complex System on Chips
  • In-depth understanding of processors and peripheral interconnect bus protocols and architectures
  • Knowledge of Verilog, System Verilog, UVM methodology
  • Self-motivated and able to work effectively both independently and in a team

Benefits For Senior Silicon Engineering

Medical Insurance
Parental Leave
401k
Education Budget
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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