ASIC Design Engineer - Clocks
Description For ASIC Design Engineer - Clocks
NVIDIA, the world leader in accelerated computing, is seeking an experienced ASIC Design Engineer for their Clocks and Resets group. This role focuses on developing next-generation Clocking implementation for Tegra SOCs, addressing the growing complexity of clocking structures with emphasis on performance and power optimization.
The position requires expertise in high-speed logic design and gate-level implementation, balancing high-frequency clocks with power optimizations, DFT, crosstalk, routing, and timing closure constraints. You'll be working with cutting-edge technology in NVIDIA's innovative environment, contributing to the development of sophisticated SOC solutions.
As an ASIC Design Engineer, you'll be involved in the complete product development lifecycle, from micro-architecture to silicon bring-up. You'll collaborate with multiple teams, implement new clocking topologies in RTL, and work on automation methodologies for efficient scaling.
NVIDIA offers a dynamic work environment where you'll be at the forefront of technological advancement in AI and digital twins, transforming major industries. The company is committed to fostering diversity and maintains an inclusive workplace culture, making it an ideal place for talented engineers looking to make a significant impact in the semiconductor industry.
Join NVIDIA to work on challenging projects that push the boundaries of what's possible in accelerated computing, while developing your expertise in advanced ASIC design and implementation.
Responsibilities For ASIC Design Engineer - Clocks
- Micro-architect and design new clocks modules and topologies for SOC support
- Evaluate trade-offs across DFX, Physical Implementation, Power Optimization and timing closure
- Collaborate with multiple SOC functions for SOC Clocking Implementation
- Work on automation and methodology for efficient Clocking RTL generation
- Participate in end-to-end SOC execution from micro-arch to Silicon bringup
- Work with CDC, RDC, Lint, Synthesis, and multi-power-domain designs
Requirements For ASIC Design Engineer - Clocks
- B.Tech or M.Tech in Electronics/VLSI or equivalent experience
- 6+ years of relevant industry work experience
- Experience in RTL design (Verilog), Gate-level Design and Synthesis
- Strong coding skills in Perl or other industry-standard scripting languages
- Excellent interpersonal skills and ability to work with multiple teams
- Understanding of sub-micron silicon issues (noise, cross-talk, OCV effects) is a bonus
- Prior experience in implementing on-chip clocking networks is a plus
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