CAD Layout Design Engineer
Description For CAD Layout Design Engineer
NVIDIA, a pioneer in GPU technology and AI innovation, is seeking a Senior CAD Layout Design Engineer to join their groundbreaking Layout Methodology team. This role combines advanced technology expertise with creative problem-solving, focusing on accelerating layout creation and improving time-to-market for NVIDIA's digital IP.
The position offers an opportunity to work at the forefront of semiconductor design, utilizing cutting-edge technology nodes and implementing machine learning techniques in layout creation. You'll be responsible for conducting technology studies, creating digital IP, and developing guidelines for EMIR and DFM, while working with advanced tools and methodologies.
The ideal candidate brings 5+ years of experience in SRAM/Analog layout design, with expertise in advanced technology nodes and strong programming skills. This role requires both technical excellence and strong communication abilities, as you'll be collaborating with various teams and influencing technological directions.
At NVIDIA, you'll be part of a company that has continuously reinvented itself over two decades, from revolutionizing computer graphics to leading the AI revolution. The company offers a diverse, supportive environment where innovation is celebrated and individual contributions make a lasting impact on the world.
Responsibilities For CAD Layout Design Engineer
- Be part of the Layout Methodology team to speed up layout creation and productivity
- Conduct in-depth study of new technology
- Create digital IP for layout work: PCELL creation, SRAM leaf cells, Productivity Scripts
- Coordinate analysis of new technology for EMIR, DFM, SRAM layout guidelines
- Investigate next generation tools for layout creation
- Investigate applications of Machine Learning/Deep Learning/LLM techniques for layout creation
Requirements For CAD Layout Design Engineer
- BE/M-Tech in Electrical & Electronics or equivalent experience
- 5+ years of experience
- Proven project cycle and tape out experience in SRAM/Analog layout design
- Experience in advanced technology nodes like 5 or 3 nanometers
- Solid proficiency in Cadence Skill language
- Solid scripting skills in Python, Perl, Shell
- Experience with EMIR tools and ability to root cause and fix EMIR issues
- Good social skills and excellent teamwork
- Excellent presentation and influencing skills
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