DFT Engineer - Hardware
Description For DFT Engineer - Hardware
NVIDIA, a pioneering technology company that revolutionized the GPU industry and parallel computing, is seeking a DFT (Design-for-Test) Engineer to join their innovative hardware team in Bengaluru. This role sits at the intersection of hardware design and testing, focusing on developing cutting-edge solutions for complex semiconductor chips.
As a DFT Engineer, you'll be working on groundbreaking innovations in test access mechanisms, IO BIST, memory BIST, and scan compression. The role offers an exciting opportunity to be part of NVIDIA's continued evolution in AI and GPU technology, working with state-of-the-art hardware designs and contributing to next-generation products.
The ideal candidate will bring a strong foundation in hardware engineering, with expertise in DFT methodologies, ASIC design flows, and verification techniques. You'll be working with multi-functional teams, requiring both technical expertise and collaborative skills. The position offers exposure to some of the industry's most complex semiconductor chips and the chance to influence testing methodologies for future NVIDIA products.
This is an excellent opportunity for a mid-level engineer with a passion for hardware design and testing to join a company at the forefront of AI and GPU technology. You'll be part of a team that values innovation and creative problem-solving, with the chance to work on projects that have a real impact on the future of computing technology.
The hybrid work environment offers flexibility while maintaining collaborative opportunities with the team. The role requires occasional travel and participation in late-hour online meetings during critical milestones, reflecting the global nature of NVIDIA's operations. If you're excited about pushing the boundaries of hardware testing and want to be part of a company that's driving the future of AI and computing, this role offers the perfect platform for your career growth.
Responsibilities For DFT Engineer - Hardware
- Design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression
- Verification and silicon bringup of Scan ATPG and other DFT features
- Develop and deploy DFT methodologies for next generation products
- Work on innovation to improve the quality of DFT methods
- Work with multi-functional teams to incorporate DFT features into the chip
- Participate in occasional travel and late hours online meetings during critical milestones
Requirements For DFT Engineer - Hardware
- BSEE or MSEE degree from reputed institutions or equivalent experience
- Well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design
- Experience in RTL and Gates verification and simulation
- Familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500
- Strong DFT knowledge in Scan ATPG, compression techniques and memory test
- Strong analytical and problem solving skills
- Good scripting knowledge (either Perl / Python)
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