Manager, Design-for-Test - ATPG

NVIDIA is the world leader in accelerated computing, pioneering solutions in AI and digital twins.
Backend
Staff Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AI · Enterprise SaaS

Description For Manager, Design-for-Test - ATPG

NVIDIA, the world leader in accelerated computing, is seeking a Manager for their Design-for-Test (DFT) Engineering team. This role involves leading a team of 10-15 engineers working on groundbreaking innovations in DFT architecture, verification, and post-silicon validation for sophisticated semiconductor chips. The position focuses on developing next-generation DFT technologies while collaborating across multiple teams including chip design, backend, verification, and production testing.

The role requires managing complex projects in parallel and implementing innovative DFT solutions that are continuously evolving to meet challenging goals. The ideal candidate will have both technical expertise in DFT/ATPG and proven leadership experience. This is an opportunity to work with cutting-edge technologies and contribute to NVIDIA's most advanced products.

The position offers exposure to groundbreaking technologies and next-generation products in an exciting and educational environment. Each team member makes significant contributions to NVIDIA's products and achievements. The company is known for attracting some of the most brilliant talent in the technology world and offers the opportunity to work on market-leading products.

Working at NVIDIA means being part of a company that's transforming the world's largest industries through AI and digital twins. The role combines technical leadership with people management, requiring both depth in DFT/ATPG knowledge and the ability to guide and develop a team of engineers. This is an ideal position for someone who wants to be at the forefront of semiconductor technology while leading and mentoring others.

Last updated 3 months ago

Responsibilities For Manager, Design-for-Test - ATPG

  • Managing a team of 10-15 ATPG/scan insertion/DFT Post Si Engineers
  • Leading the development of next generation DFT technologies
  • Coordinating multi projects execution in parallel
  • Leading automation flows and processes that provide short test time to production
  • Working closely with chip design, backend, verification, and production testing teams

Requirements For Manager, Design-for-Test - ATPG

  • 2+ years of proven management experience in the DFT field
  • 5+ years of hands-on DFT/ATPG experience
  • BSc. in Electrical Engineering or Computer engineering
  • Knowledge of DFT/ATPG tools
  • Quick learner, proactive and self-motivated
  • Sense of ownership, commitment, and responsibility

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