Senior ASIC Design Engineer
Description For Senior ASIC Design Engineer
NVIDIA is seeking a Senior ASIC Design Engineer to join their digital logic interconnect design team. This role focuses on implementing logic for next-generation GPU's and SOCs that enable high-performance interconnect of multi-GPU/CPU/DPU system topologies. The position involves working on cutting-edge solutions for autonomous machines, Cloud and Data Centers, Deep learning, High-Performance Computing, Gaming, and Entertainment.
The ideal candidate will be responsible for micro-architectural definition, RTL coding, logic debug, timing closure, power optimization and verification support. They should have extensive experience with PCIE Physical/Data-Link Layer or other industry standard protocols like CXL, AXI, CHI, UCIe USB, and SATA.
Working at NVIDIA means joining one of the technology world's most desirable employers, with some of the most forward-thinking and hardworking people in the industry. The role offers competitive compensation, including a base salary range of $164,000 - $304,750 USD, equity, and comprehensive benefits.
The position requires strong technical skills in ASIC design, particularly in areas such as data scrambling, packet framing, NRZ/PAM4 encoding, and equalization. The successful candidate will collaborate with cross-functional teams, lead junior engineers, and contribute to the development of next-generation computing platforms that drive NVIDIA's success in this rapidly growing field.
This hybrid role is based in the Boston area and offers the opportunity to work on challenging projects that push the boundaries of computing technology. NVIDIA maintains a strong commitment to diversity and inclusion, fostering an environment where innovation and creativity can thrive.
Responsibilities For Senior ASIC Design Engineer
- Micro architecting the next generation of PCIE PL and DL
- Implementing readable, high-performance, area and power efficient RTL
- Collaborating with architects, external partners, software engineers and circuit designers
- Partnering with Physical Design team on partitioning, floorplanning and timing closure
- Providing design documentation, triaging and debugging functional and performance bugs
- Leading junior engineers and assisting management with task assignments
Requirements For Senior ASIC Design Engineer
- Bachelors Degree in EE, CS or CE or equivalent experience
- 8+ years of relevant experience or an Advanced Degree with equivalent experience
- 5+ years experience in coding PCIE PL/DL logic
- In-depth understanding of physical design
- Strong working knowledge of Verilog or System Verilog
- Strong collaboration and communication skills
Benefits For Senior ASIC Design Engineer
- Equity
- Comprehensive benefits package
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