Senior ASIC Physical Design Engineer, Netlisting
Description For Senior ASIC Physical Design Engineer, Netlisting
NVIDIA, a pioneer in GPU technology and AI computing, is seeking a Senior ASIC Physical Design Engineer specializing in Netlisting. This role is crucial for the company's continued innovation in high-performance computing hardware. The position involves sophisticated work with CPUs, GPUs, and SoCs, focusing on critical aspects of physical design and netlist management.
The role offers an opportunity to work at the cutting edge of hardware design, contributing to NVIDIA's groundbreaking work in AI and parallel computing. The successful candidate will be responsible for driving physical design of high-frequency and low-power processors, managing complex timing constraints, and ensuring quality through various checking mechanisms.
This position requires a strong background in electrical or computer engineering, with extensive experience in logic equivalence checking, hardware architecture, and timing analysis. The ideal candidate will possess both technical expertise and problem-solving skills, with the ability to work with industry-standard EDA tools and programming languages.
NVIDIA offers competitive compensation, including a substantial base salary range and equity benefits. The company's culture emphasizes creativity, autonomy, and continuous learning, making it an ideal environment for engineers who want to push the boundaries of what's possible in hardware design.
Join NVIDIA's team of forward-thinking professionals and be part of a company that has consistently reinvented itself and led technological advancement for over two decades. This role presents an excellent opportunity to contribute to cutting-edge technology that shapes the future of AI and computing.
Responsibilities For Senior ASIC Physical Design Engineer, Netlisting
- Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level
- Focus on netlist-related aspects including equivalence checking, asynchronous checking, clock domain crossing checks and MTBF analysis
- Handle logic synthesis and netlist quality checks
- Drive timing convergence and constraints generation/management
- Implement ECO generation
Requirements For Senior ASIC Physical Design Engineer, Netlisting
- BS in Electrical or Computer Engineering with 5 years' experience or MS with 2 years' experience
- Expertise in logic equivalence checking/FV from RTL to tapeout
- Deep understanding of hardware architecture and RTL/logic design for timing closure
- Experience in clock-domain-crossing checking and MTBF analysis
- Background with logic synthesis at block or full-chip level
- Strong experience in Static Timing Analysis (STA)
- Expertise in industry standard EDA tools
- Proficiency in programming and scripting languages (Perl, TCL, Make, Python)
Benefits For Senior ASIC Physical Design Engineer, Netlisting
- Equity
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