Senior ASIC Physical Design Engineer, Netlisting
Description For Senior ASIC Physical Design Engineer, Netlisting
NVIDIA, a pioneer in GPU technology and AI computing, is seeking a Senior ASIC Physical Design Engineer specializing in Netlisting. This role is crucial for the company's continued innovation in high-performance computing hardware. The position involves sophisticated work with CPUs, GPUs, and SoCs, focusing on critical aspects of physical design and netlist management.
The role offers an opportunity to work at the cutting edge of hardware design, contributing to technology that powers AI, gaming, and parallel computing innovations. You'll be responsible for complex tasks including equivalence checking, timing analysis, and logic synthesis, requiring both technical expertise and strategic thinking.
NVIDIA's culture emphasizes innovation and autonomous work, making it an ideal environment for creative problem-solvers. The company has a strong track record of technological breakthroughs, from inventing the GPU in 1999 to leading the current AI computing revolution.
The position offers competitive compensation, including a substantial base salary range, equity, and comprehensive benefits. You'll join a team of forward-thinking professionals in Santa Clara, contributing to projects that significantly impact the technology industry. This role is perfect for experienced engineers who want to push the boundaries of hardware design while working for a recognized leader in AI and accelerated computing.
Responsibilities For Senior ASIC Physical Design Engineer, Netlisting
- Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and full chip level
- Focus on netlist-related aspects including equivalence checking, asynchronous checking, clock domain crossing checks and MTBF analysis
- Handle logic synthesis and netlist quality checks
- Drive timing convergence and constraints generation/management
- Implement ECO generation and implementation
Requirements For Senior ASIC Physical Design Engineer, Netlisting
- BS in Electrical or Computer Engineering with 5 years experience or MS with 2 years experience
- Expertise in logic equivalence checking/FV from RTL to tapeout
- Deep understanding of hardware architecture and RTL/logic design for timing closure
- Experience in clock-domain-crossing checking and MTBF analysis
- Background with logic synthesis at block or full-chip level
- Strong experience in Static Timing Analysis (STA)
- Expertise in industry standard EDA tools
- Proficiency in programming languages like Perl, TCL, Make, Python
Benefits For Senior ASIC Physical Design Engineer, Netlisting
- Competitive base salary
- Equity compensation
- Comprehensive benefits package
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