Senior ASIC Timing Engineer

NVIDIA is the world leader in accelerated computing, pioneering GPU and AI technologies.
$168,000 - $310,500
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
8+ years of experience
AI · Enterprise SaaS

Description For Senior ASIC Timing Engineer

NVIDIA, a global leader in accelerated computing and AI technology, is seeking a Senior ASIC Timing Engineer to join their Networking Silicon engineering team. This role is crucial in developing industry-leading high-speed communication devices that deliver maximum throughput and minimal latency. The position offers an opportunity to work on groundbreaking chip development in a professional, growth-oriented environment.

The ideal candidate will be responsible for driving physical design and timing of high-frequency and low-power DPUs and SoCs, working at block, cluster, and full chip levels. This role requires extensive experience in synthesis and timing, with a strong background in electrical or computer engineering. The position demands expertise in analyzing crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

NVIDIA has a rich history of innovation, from inventing the GPU in 1999 to revolutionizing AI through GPU deep learning. The company offers competitive compensation, including a substantial base salary range of $168,000 - $310,500, plus equity and comprehensive benefits. This is an excellent opportunity to join a company that's at the forefront of AI computing and consistently ranked as one of the technology world's most desirable employers.

The role combines technical expertise with collaborative teamwork, making it ideal for someone who is both technically proficient and a great team player. You'll be working with some of the most forward-thinking professionals in the industry, contributing to technologies that are shaping the future of computing and AI.

Last updated a day ago

Responsibilities For Senior ASIC Timing Engineer

  • Drive physical design and timing of high-frequency and low-power DPUs and SoCs at multiple levels
  • Analyze and optimize design constraints and synthesis parameters
  • Drive frontend and backend implementation from RTL to gds2
  • Handle timing and power convergence, and ECO implementation

Requirements For Senior ASIC Timing Engineer

Python
  • BS in Electrical or Computer Engineering (or equivalent experience)
  • 8+ years experience or MS with 2 years experience in Synthesis and Timing
  • Understanding of DFT logic and hands-on experience in design closure
  • Expertise in analyzing crosstalk delay, noise glitch, and electrical/manufacturing rules
  • Knowledge in process variation effect modeling
  • Experience in critical path planning
  • Proficiency in Static Timing tools like Synopsys PrimeTime or Cadence Tempus
  • Solid experience in Static Timing Analysis (STA)
  • Proficiency in Python, Tcl and Make for automation and scripting

Benefits For Senior ASIC Timing Engineer

Equity
  • Equity

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