Senior ASIC Timing Engineer
Description For Senior ASIC Timing Engineer
NVIDIA, a global leader in accelerated computing and AI technologies, is seeking a Senior ASIC Timing Engineer to join their Networking Silicon engineering team. This role is crucial in developing industry-leading high-speed communication devices that deliver maximum throughput and minimal latency.
The position offers an opportunity to work on groundbreaking chip development in a technology-focused environment where innovation is paramount. As a Senior ASIC Timing Engineer, you'll be responsible for driving physical design and timing of high-frequency and low-power DPUs and SoCs at various levels, from block to full chip implementation.
NVIDIA's legacy includes inventing the GPU in 1999, which transformed the PC gaming market and modern computer graphics. The company has since evolved into a key player in AI and deep learning, consistently pushing the boundaries of technological innovation. Their commitment to solving complex challenges that matter to the world makes this role particularly impactful.
The ideal candidate will bring extensive experience in synthesis and timing, with strong expertise in static timing analysis and design closure. You'll work with cutting-edge tools and technologies, contributing to projects that shape the future of computing. The position offers competitive compensation, including a substantial base salary range of $168,000 - $310,500, plus equity and comprehensive benefits.
NVIDIA's culture emphasizes creativity, autonomy, and continuous learning, making it one of the technology sector's most sought-after employers. The company values diversity and maintains an inclusive work environment, making it an ideal place for professionals looking to make a significant impact in the semiconductor industry.
Responsibilities For Senior ASIC Timing Engineer
- Drive physical design and timing of high-frequency and low-power DPUs and SoCs
- Analyze and optimize design constraints and synthesis parameters
- Drive frontend and backend implementation from RTL to gds2
- Handle timing constraints, timing and power convergence, and ECO implementation
Requirements For Senior ASIC Timing Engineer
- BS in Electrical or Computer Engineering (or equivalent experience)
- 8+ years experience or MS with 2 years experience in Synthesis and Timing
- Understanding of DFT logic and hands-on experience in design closure
- Expertise in analyzing crosstalk delay, noise glitch, and electrical/manufacturing rules
- Knowledge in process variation effect modeling
- Experience in critical path planning
- Proficiency in Static Timing tools like Synopsys PrimeTime or Cadence Tempus
- Solid experience in Static Timing Analysis (STA)
- Proficiency in Python, Tcl and Make for automation and scripting
Benefits For Senior ASIC Timing Engineer
- Competitive base salary
- Equity compensation
- Comprehensive benefits package
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