Senior ASIC Timing Engineer
Description For Senior ASIC Timing Engineer
NVIDIA, the pioneer in GPU technology and AI computing, is seeking a Senior ASIC Timing Engineer to join their Networking Silicon engineering team. This role is crucial in developing industry-leading high-speed communication devices that deliver maximum throughput and minimal latency. The position offers an opportunity to work on groundbreaking chip development in a technology-focused environment.
The role involves sophisticated timing design work on DPUs and SoCs, requiring expertise in both physical design and timing analysis. You'll be working with cutting-edge technology, handling complex timing constraints, and ensuring optimal performance of NVIDIA's innovative hardware solutions.
As a Senior ASIC Timing Engineer, you'll be part of NVIDIA's journey in revolutionizing parallel computing and advancing AI technology. The company has a strong track record of continuous innovation, from inventing the GPU in 1999 to leading the AI computing revolution today.
The position offers competitive compensation, including a substantial base salary range and equity benefits. NVIDIA's commitment to fostering a diverse work environment and its status as one of the technology world's most desirable employers make this an exceptional opportunity for experienced timing engineers looking to make a significant impact in the semiconductor industry.
The ideal candidate will combine technical expertise in timing analysis and design closure with strong collaboration skills, contributing to NVIDIA's mission of amplifying human inventiveness and intelligence through technology.
Responsibilities For Senior ASIC Timing Engineer
- Drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and full chip level
- Analyze and optimize design constraints and synthesis parameters
- Drive frontend and backend implementation from RTL to gds2
- Handle timing constraints, timing and power convergence, and ECO implementation
Requirements For Senior ASIC Timing Engineer
- BS in Electrical or Computer Engineering (or equivalent experience)
- 8+ years experience or MS with 2 years experience in Synthesis and Timing
- Understanding of DFT logic and hands-on experience in design closure
- Expertise in analyzing crosstalk delay, noise glitch, and electrical/manufacturing rules
- Knowledge in process variation effect modeling
- Experience in critical path planning
- Proficiency in Static Timing tools like Synopsys PrimeTime or Cadence Tempus
- Solid experience in Static Timing Analysis (STA)
- Proficiency in Python, Tcl and Make for automation and scripting tasks
Benefits For Senior ASIC Timing Engineer
- Equity
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