Senior ASIC Timing Engineer
Description For Senior ASIC Timing Engineer
NVIDIA, a pioneer in GPU technology and AI computing, is seeking a Senior ASIC Timing Engineer to join their dynamic team. Since inventing the GPU in 1999, NVIDIA has been at the forefront of technological innovation, revolutionizing parallel computing and igniting the modern AI era. The role involves crucial responsibilities in timing analysis and closure for NVIDIA's cutting-edge processors, working with various teams to ensure optimal performance.
The position offers an opportunity to work on some of the most advanced computing technologies in the industry, from GPUs to CPUs and DPUs. You'll be part of a team that drives timing analysis and closure at multiple levels, from block to full chip implementation. The role requires expertise in Static Timing Analysis (STA) and deep sub-micron process nodes, making it perfect for someone who wants to push the boundaries of semiconductor technology.
NVIDIA is known for being one of the technology world's most desirable employers, offering competitive compensation including equity and comprehensive benefits. The company values creativity and autonomy, making it an ideal environment for engineers who want to make a significant impact in the field of AI computing and chip design. This role represents a chance to be part of a company that consistently reinvents itself and tackles challenges that matter to the world.
Responsibilities For Senior ASIC Timing Engineer
- Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level
- Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy
- Create timing constraints, driving timing and power convergence, and ECO implementation
- Improve timing convergence flows working with the methodology teams
Requirements For Senior ASIC Timing Engineer
- BS in Electrical or Computer Engineering with 5 years experience or MS with 2 years experience in Timing and STA
- Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence
- Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis
- Expertise in industry standard STA and timing convergence tools
- Knowledge of deep sub-micron process nodes
Benefits For Senior ASIC Timing Engineer
- Equity
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