Senior ASIC Verification Engineer

NVIDIA is seeking a Senior ASIC Verification Engineer to join their Power Management Unit (PMU) IP team. As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. NVIDIA's PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic, collecting and processing data from the entire chip to determine optimal operating points.

Responsibilities:

• Collaborate with IP architects and designers to define IP verification methodology and test plans
• Complete IP verification for new features across projects
• Maintain and improve SystemVerilog-based unit-level testbenches for power and efficiency
• Maintain regression tests and run various sign-off verification checklists
• Learn and practice formal verification, using formal tools to assist simulation and raise verification quality

Requirements:

• BS with 5+ years of experience or MS with 3+ years of working experience
• Self-driven, active thinking, and problem-solving skills
• Solid IC background
• Experience with SystemVerilog and UVM methodology
• Familiarity with Perl or Python scripting
• Familiarity with C/C++ coding

Preferred Qualifications:

• Experience building complex testbenches from scratch
• Proficiency in solving environment issues (e.g., setting up Makefiles, resolving VCS issues)
• Strong communication skills with the ability to state problems clearly
• Excellent oral and written English skills

Join NVIDIA's innovative team and contribute to the development of cutting-edge power management solutions that drive efficiency across various computing applications.