Senior Chip Design Verification Engineer
Description For Senior Chip Design Verification Engineer
NVIDIA is seeking a Senior Chip Design Verification Engineer to join their Network Adapter Silicon group, focusing on developing industry-leading high-speed smart communication devices and Data Processing Units (DPU). This role is integral to the verification and design of groundbreaking chips, offering an opportunity to work in a technology-focused environment with significant impact. The position involves working with cutting-edge verification methodologies and tools, requiring expertise in chip design verification and network protocols. The ideal candidate will have experience with high-speed interconnects, smart NIC and/or SoC, and knowledge of Specman and Verilog. This role offers the chance to work with some of the most forward-thinking professionals in the industry, contributing to NVIDIA's mission of crafting the highest performance and lowest power silicon possible. The position combines technical expertise with collaborative teamwork, making it ideal for someone who thrives in a challenging, innovative environment focused on pushing the boundaries of technology.
Responsibilities For Senior Chip Design Verification Engineer
- Work in a verification team developing Networking silicon core units
- Build reference models, verify and simulate chip blocks/entities according to specifications
- Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FW
Requirements For Senior Chip Design Verification Engineer
- B.Sc. or above in Electrical Engineering or Computer Engineering
- 5+ years of validated experience
- Professional verification experience, knowledge in advanced verification methodologies and tools
- Strong debugging, problem solving and analytical skills
- Demonstrates deep understanding in design and verification logic
- Self-motivated, ability to work independently and drive tasks to completion
- Team player with excellent communication and interpersonal skills
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