Senior High-Performance ASIC Timing Engineer
Description For Senior High-Performance ASIC Timing Engineer
NVIDIA, a pioneer in GPU technology and AI computing, is seeking a Senior High-Performance ASIC Timing Engineer to join their innovative team. This role is crucial in developing and executing timing closure plans for NVIDIA's next-generation high-performance IPs across CPU, GPU, and SOC designs.
The position offers an opportunity to work at the forefront of technology, where your expertise in static timing analysis and high-performance design convergence will directly impact NVIDIA's cutting-edge products. You'll be responsible for comprehensive timing aspects, including constraints setup, analysis, closure, and methodology development.
NVIDIA's legacy includes revolutionizing the PC gaming market with the invention of the GPU in 1999 and leading the modern AI revolution through GPU deep learning. As a "learning machine," NVIDIA continuously evolves by taking on challenging opportunities that matter to the world.
The ideal candidate will bring strong technical expertise in ASIC design and timing, with either a BS and 5+ years of experience or an MS with 3+ years of experience. Your proficiency in programming languages like Python, Perl, and Tcl, combined with hands-on experience in STA tools and ECO implementation, will be essential for success in this role.
The position offers a competitive salary range of $136,000 - $264,500, along with equity and comprehensive benefits. Located in Santa Clara, CA, you'll be working at the heart of Silicon Valley, contributing to technology that transforms industries and amplifies human intelligence and creativity.
Join NVIDIA's team of forward-thinking professionals and be part of a company that's widely considered to be the leader in AI computing and one of the technology world's most desirable employers. This role offers the perfect blend of technical challenge and innovative opportunity for those passionate about high-performance computing and timing engineering.
Responsibilities For Senior High-Performance ASIC Timing Engineer
- Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, GPU and SOC designs
- Owning static timing analysis and convergence of high-performance designs
- Responsible for timing constraints, timing analysis and closure, ECO implementation, and timing methodologies
- Finding the right tradeoffs between power/area/congestions
Requirements For Senior High-Performance ASIC Timing Engineer
- BS in Electrical or Computer Engineering with 5+ years' experience or MS with 3+ years' experience in ASIC Design and Timing
- Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs
- Strong background in timing constraints generation, clocking, process variations and signal integrity
- Proficiency in programming and scripting languages (Perl, Tcl, Python)
- Familiarity with methodology and tools, logic synthesis, equivalence checking
- Strong interpersonal and communication skills
- Strong understanding of timing and physical design fundamentals
Benefits For Senior High-Performance ASIC Timing Engineer
- Equity
- Benefits package available
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