Senior Package Layout Engineer

NVIDIA Networking unit is seeking a Senior IC Packaging Design Engineer to join their package team. The role focuses on delivering and designing state-of-the-art high-speed Interconnect systems for Supercomputers and Datacenters. As part of the IC Packaging design team, you will collaborate to implement high-speed and PDN design for ASIC packages.

Key responsibilities include:

• Developing symbols, pad stack, and performing substrate package routing, placement, stack-up, reference plane, and power distribution using Cadence APD or SiP tools.
• Optimizing package pin out incorporating system-level trade-offs of pins assignment.
• Developing methodologies to improve layout environment, productivity, reliability, and schedule considerations.
• Working closely with SI/PI/HW design teams and product teams.
• Planning, ensuring stakeholder management, and leading projects from start to finish.

Requirements:

• B.Sc. Electrical Engineering or an Electrical Practical Engineer certificate or equivalent experience.
• 5+ years hands-on experience in Package/PCB Layout and routing, including high-speed design signal integrity practices.
• Experience in substrate layout of wire bond and flip chip packages (preferred).
• Knowledge of substrates or board manufacturing process.
• Significant background with Cadence Virtuoso and APD or SiP and/or other PCB layout tools.

Additional skills that would be advantageous:

• Knowledge of Ansys (SIwave, HFSS) or Cadence (Sigrity, PowerSI) simulation tools.
• Familiarity with Skill language (Cadence) and basic parsing abilities (Python/Perl/Shell-scripting).

NVIDIA offers a dynamic work environment with some of the most forward-thinking and hardworking people in the world. They are committed to fostering diversity and do not discriminate based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other protected characteristic.