Senior Photonic Layout Design Engineer
Description For Senior Photonic Layout Design Engineer
NVIDIA Analog Layout design team is seeking a Senior Photonic Layout Design Engineer to join a growing group focused on developing new silicon photonic devices and handling challenges in high-speed mixed-signal circuit designs.
NVIDIA, founded in 1999 with the invention of the GPU, has continuously reinvented itself over two decades. The company has played a pivotal role in the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, NVIDIA's GPU deep learning has ignited modern AI, ushering in a new era of computing.
As a Senior Photonic Layout Design Engineer, you will be responsible for:
- Planning and implementing high-speed electro-optical and mixed-signal analog layout designs in state-of-the-art sub-micron SiPh, CMOS, and FinFET technologies using Cadence tools
- Performing physical layout for electro-optic and mixed-signal functions like PLLs, high-speed I/O circuits, SerDes, general I/Os, and ESD structures
- Collaborating with electro-optics and mixed-signal engineers to customize designs for integration in photonic and VLSI products
- Floor planning, custom layout, verifying against design rules and schematics, and conducting EM/IR analysis
The ideal candidate should have:
- Minimum 7 years of relevant mask analog layout experience
- B.Sc. in Electrical Engineering or an Electronics Practical Engineer certificate
- Familiarity with silicon photonics layout design concepts
- Proven understanding of analog circuit layout concepts in submicron CMOS technologies
- Expertise with Cadence custom circuit design tools, particularly Virtuoso
- Experience running and debugging DRC and LVS with verification tools such as ICV and Calibre
- Strong teamwork and interpersonal skills
Additional skills that would be advantageous include:
- Experience with electro-optical ASIC layout
- Previous responsibility for ramping up new process nodes
- Proficiency in scripting languages like Python, Skill, and Pcell writing
- Knowledge of DRC and LVS checking flows, EM/IR tools, and ability to customize DRC and LVS decks
Join NVIDIA's ASIC Security team and contribute to building the real-time, cost-effective computing platform driving success across several exciting and rapidly growing fields.
Responsibilities For Senior Photonic Layout Design Engineer
- Planning and implementation of high-speed electro-optical and mixed-signal analog layout designs in state-of-the-art sub-micron SiPh, CMOS, FinFET technologies using Cadence tools
- Perform physical layout for electro-optic and mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs
- Work with electro-optics and mixed-signal engineers to customize designs for integration in photonic and VLSI products
- Floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis
Requirements For Senior Photonic Layout Design Engineer
- Minimum 7 years of relevant mask analog layout experience
- B.Sc. in Electrical Engineering or an Electronics Practical Engineer certificate
- Familiar with silicon photonics layout design concepts
- Proven understanding of analog circuit layout concepts in submicron CMOS technologies
- Expert with Cadence custom circuit design tools - particularly Virtuoso
- Experience running and debugging DRC and LVS with verification tools such as ICV, Calibre
- Work effectively in a team, with good interpersonal skills, enthusiasm, and positive energy
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