Senior Physical Design Engineer

NVIDIA is the world leader in accelerated computing, pioneering GPU technology and AI solutions.
$196,000 - $356,500
Embedded
Senior Software Engineer
In-Person
12+ years of experience
AI · Enterprise SaaS · Hardware

Description For Senior Physical Design Engineer

NVIDIA, the pioneer of GPU technology and leader in accelerated computing, is seeking a Senior Physical Design Engineer to join their innovative team. This role is crucial in developing next-generation GPU and ASIC technologies for desktop, laptop, workstation, and mobile markets. With over two decades of continuous innovation, NVIDIA has transformed from a gaming graphics company to a full-stack computing company powering AI and digital twins across industries.

The position offers an opportunity to work on cutting-edge technology at 5nm, 4nm, and 3nm nodes, requiring expertise in physical design implementation, timing analysis, and power optimization. You'll be part of a team establishing design methodologies and handling complex chip implementations from floorplanning to final tape-out.

The ideal candidate brings 12+ years of experience in VLSI physical design, with a proven track record of production deliveries. Your expertise in CAD tools from industry leaders like Synopsys, Cadence, and Mentor Graphics will be essential for success. The role combines technical depth in custom macro blocks with broad knowledge of modern chip design workflows.

NVIDIA offers competitive compensation with a base salary range of $196,000 to $356,500, plus equity and comprehensive benefits. Join a company that's at the forefront of AI computing and consistently ranked as one of the most desirable employers in the technology sector. This is an opportunity to work with forward-thinking professionals and contribute to technologies that are transforming industries worldwide.

Last updated 18 days ago

Responsibilities For Senior Physical Design Engineer

  • Responsible for all aspects of physical design and implementation of GPU and other ASICs
  • Establish physical design methodologies, flow automation, chip floorplan, power/clock distribution
  • Participate in chip assembly and P&R, timing closure
  • Craft designs for static timing analysis, power and noise analysis and back-end verification

Requirements For Senior Physical Design Engineer

Python
  • BSEE (MSEE preferred) or equivalent experience
  • 12+ years of experience in large VLSI physical design implementation on 5nm, 4nm and 3nm technology
  • Successful track record of delivering designs to production
  • Experience in Power, Performance and Area improvement Initiatives
  • Strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools
  • Deep understanding of custom macro blocks
  • Experience in timing closure, clock/power distribution and analysis
  • Strong analytical and debugging skills
  • Proficiency using Python, Perl, Tcl, Make scripting

Benefits For Senior Physical Design Engineer

Equity
  • Equity
  • Benefits Package

Interested in this job?

Jobs Related To NVIDIA Senior Physical Design Engineer

Senior Firmware PHY Verification Engineer

Senior Firmware PHY Verification Engineer role at NVIDIA, focusing on firmware verification, networking features, and automation with C/C++ and Linux expertise required.

Senior System Level Product Engineer

Senior System Level Product Engineer role at NVIDIA, focusing on post-silicon validation and system level testing for industry-leading GPU and SOC products.

Senior Firmware Engineer - Embedded Controller

Senior Firmware Engineer position at NVIDIA focusing on embedded controller development, requiring 5+ years experience in firmware development and strong programming skills.

Senior Power and Thermal Engineer

Senior Power and Thermal Engineer role at NVIDIA focusing on next-generation power management solutions and system architecture optimization.

Senior Silicon Low Power Development Engineer

Senior Silicon Low Power Development Engineer role at NVIDIA, focusing on developing and architecting power-saving features for silicon and system-level implementations.