Senior RTL Analysis Methodology Engineer
Description For Senior RTL Analysis Methodology Engineer
NVIDIA, a pioneer in accelerated computing for over 25 years, is seeking a Senior RTL Analysis Methodology Engineer to join their dynamic team. This role is crucial in developing and maintaining RTL CDC and RDC methodology for NVIDIA's semiconductor products. The position offers an opportunity to work with cutting-edge technology in AI computing and chip design.
The role involves developing flows and methodologies for Clock Domain Crossing and Reset Domain Crossing, working with state-of-the-art EDA tools, and serving as a bridge between designers and EDA vendors. You'll be responsible for inventing new methodologies, implementing automation solutions, and ensuring quality through regression testing and analysis.
As an ideal candidate, you should have extensive experience in RTL analysis, design, and verification, with strong programming skills in languages like Python, Perl, and Tcl. Knowledge of Verilog SystemVerilog HDL and experience with commercial RTL analysis tools is essential.
NVIDIA offers competitive compensation, including a base salary range of $136,000 - $264,500, plus equity and benefits. The company is committed to fostering diversity and innovation, making it an ideal workplace for creative and autonomous professionals who want to make a lasting impact in AI and accelerated computing.
Responsibilities For Senior RTL Analysis Methodology Engineer
- Develop flows, methodology, and application support for Clock Domain Crossing(CDC), Reset Domain Crossing(RDC)
- Develop leading-edge CAD flow for EDA tools
- Evaluate, deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis
- Act as liaison between designers and EDA vendors
- Invent new methodologies to improve coverage and user efficiency
- Write technical documents and train internal users
- Set up and maintain flow regressions and QA
- Employ data collection, analysis, and reporting tools
Requirements For Senior RTL Analysis Methodology Engineer
- BS or MS in Electrical Engineering, Computer Engineering, or related fields
- BS with 6+ years, or MS with 4+ years of experience in RTL analysis, RTL design, and verification
- Deep understanding of static sign-off technologies CDC, RDC and Formal
- Proficiency in scripting languages (Perl, Python, Tcl) and Make
- Proficiency in Verilog SystemVerilog HDL
- Excellent problem solving and debugging skills
- Strong interpersonal and collaboration skills
Benefits For Senior RTL Analysis Methodology Engineer
- Equity
- Benefits package available
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