Senior VLSI Physical Design Integration Engineer
Description For Senior VLSI Physical Design Integration Engineer
NVIDIA, a global leader in accelerated computing and AI technology, is seeking a Senior VLSI Physical Design Integration Engineer to join their team. This role offers an exciting opportunity to work on cutting-edge semiconductor technology at one of the world's most innovative companies.
The position involves working with teams across the USA, Israel, and India, contributing to NVIDIA's networking product line from concept to tapeout. The role combines technical expertise in VLSI design with collaborative teamwork, making it ideal for someone who enjoys both technical challenges and cross-functional collaboration.
As a Senior VLSI Physical Design Integration Engineer, you'll be responsible for critical aspects of chip design, including RTL integration, connectivity checks, synthesis workflows, and physical design flow optimization. The role requires expertise in advanced node technologies (16nm to 3nm) and proficiency with industry-standard EDA tools from Synopsys and Cadence.
NVIDIA offers a competitive compensation package with a base salary range of $136,000 to $264,500 USD, plus equity and benefits. The company is known for its innovative culture and commitment to pushing technological boundaries, particularly in AI computing and parallel processing.
The ideal candidate will bring 5+ years of relevant experience, strong analytical skills, and programming proficiency in languages like Python, Perl, and Tcl. This role offers the opportunity to work on challenging projects that impact the future of computing technology while being part of a team that has continuously reinvented itself over two decades.
NVIDIA's commitment to diversity and inclusion, combined with its position as a leader in AI computing, makes this an excellent opportunity for someone looking to advance their career in semiconductor design while working on technology that matters to the world.
Responsibilities For Senior VLSI Physical Design Integration Engineer
- Run integration flows to build RTL, run connectivity checks, and assemble logical units
- Perform linting checks and debug RTL and netlist-level issues
- Collaborate with front-end teams to resolve connectivity issues
- Project level cell library management
- Run synthesis workflows and optimize for area, power, and timing
- Run physical design flow from netlist to GDS, perform STA, physical verification (LVS/DRC)
- Perform netlist checks and formal equivalence validation
- Enhance tool automation, streamline workflows, and document best practices
Requirements For Senior VLSI Physical Design Integration Engineer
- BSEE / MSEE or equivalent experience
- Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology
- Able to assist in design flow development and debugging
- Strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools
- Strong analytical and debugging skills
- Proficiency using Python, Perl, Tcl, Make scripting
- Great teammate
Benefits For Senior VLSI Physical Design Integration Engineer
- Equity
- Additional benefits available but not specified in the posting
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