Software Development Intern

Java is one of the most popular programming languages in the world and it runs on billions of devices scaling from credit cards to multi-machine servers. Oracle is the main contributor to the Java programming language, developed through the OpenJDK project. The Java Virtual Machine (JVM) is the core piece of technology that enables Java's "write once, run anywhere" - the ability to run the same Java program on multiple hardware architectures and operating systems without having to recompile the code.

The JVM also implements the Java memory management with Garbage Collectors (GCs) that handle all the details for you, and just-in-time (JIT) compilers that enable Java performance to be better than what is possible with any statically compiled language. We are now looking for talented, purpose-focused, and highly motivated collaborators for an internship in the Stockholm development office.

The goal of this project is to achieve faster compilation times, more precise GC barrier elision opportunities, more maintainable and less fragile code, possibly even more efficient GC barrier implementations by going lower level than a CPU agnostic IR, and hopefully getting to a more standardized way of emitting GC barriers instead of all GCs doing different things as it is today.

This will be achieved by building a GC barrier infrastructure for the G1 GC similar to what has already been done for Generational ZGC. GC barriers are machine code instructions used to help perform bookkeeping required to maintain invariants. This project involves injecting the machine instructions for GC barriers at the very late instruction emission phase of the C2 JIT compiler, instead of the very early bytecode parsing phase where it is emitted today.

By emitting the GC barriers very early as done today, optimization phases throughout the compilers (e.g. escape analysis) currently needs to recognize that it should do something different for GC barrier Intermediate Representation (IR) nodes, as opposed to general application IR. The new approach doesn't add any IR nodes for the GC barriers at all, and hence doesn't introduce such complexity to the compiler design. The new feature should be implemented for the x64 and aarch64 CPU targets, likely to involve low level architecture specific optimization of the machine instruction sequences, as well as high level optimizations on the IR level to elide unnecessary GC barriers.

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