EVA/Video Design Verification Engineer

A leading technology company specializing in multimedia video and computer vision hardware design and development.
Backend
Mid-Level Software Engineer
Hybrid
2+ years of experience
AI

Description For EVA/Video Design Verification Engineer

Qualcomm is seeking a talented EVA/Video Design Verification Engineer to join their Multimedia Video and Computer Vision HW Design team in Cork, Ireland. This role offers a unique opportunity to work on cutting-edge Video CODEC Standards and Advanced Computer Vision applications.

The position combines flexible work options, including both remote work and time in Qualcomm's state-of-the-art office in Penrose Dock, Cork. As a Verification Engineer, you'll be responsible for understanding and verifying multimedia designs, specifically video encoder/decoder and CV hardware IP and subsystem functionality.

You'll work alongside architects, ASIC designers, and SW engineers to plan and execute verification and validation of multimedia subsystems for integration into SoCs for mobile applications. The role involves creating test benches, implementing verification environments, and collaborating across multiple teams to ensure robust system validation.

Key responsibilities include architecting verification solutions, maintaining test environments in System Verilog/UVM, and participating in micro-architecture reviews. You'll also be involved in automation development and technical documentation.

Qualcomm offers an excellent benefits package including stock options, performance bonuses, comprehensive insurance coverage, and various wellness programs. The company maintains a strong focus on work-life balance and professional development, providing opportunities for growth and innovation in a collaborative, cutting-edge environment.

The position requires a minimum of 2 years of DV experience and expertise in various verification technologies. This role is perfect for someone passionate about multimedia systems and verification who wants to contribute to next-generation mobile technologies while working with a global leader in semiconductor technology.

Last updated 2 months ago

Responsibilities For EVA/Video Design Verification Engineer

  • Architect, design, and implement testbenches to verify computer vision IPs
  • Create and maintain verification test benches in System Verilog/UVM
  • Collaborate with Architecture, Software, Firmware, Design teams
  • Participate in micro-architecture reviews
  • Build automation for continuous integration and testing
  • Write technical documentation

Requirements For EVA/Video Design Verification Engineer

Python
Java
  • Minimum 2 years of DV experience using UVM/assertion based verification
  • Experience in verifying complex SOC or SOC subsystems
  • Experience with caches and DDR memory protocol verification
  • Exposure to firmware/driver development using C++
  • Experience with Power aware simulations
  • Experience with Gate level Simulations

Benefits For EVA/Video Design Verification Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
Equity
Parental Leave
Relocation Benefits
  • Flexible work options
  • Stock and performance related bonus
  • Maternity/Paternity Leave
  • Employee stock purchase scheme
  • Matching pension scheme
  • Education Assistance
  • Relocation and immigration support
  • Life, Medical, Income and Travel Insurance
  • Subsidised memberships for physical and mental well-being
  • Bicycle purchase scheme

Interested in this job?

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