Sensor Subsystem Design Verification Engineer
Description For Sensor Subsystem Design Verification Engineer
QT Technologies Ireland Limited is seeking a talented Sensor Subsystem Design Verification Engineer to join our team in Cork, Ireland. This role offers an exciting opportunity to work with cutting-edge sensor technologies embedded in smartphones, automotive, IoT, smartwatches, and other consumer electronics devices.
As a Design Verification Engineer, you'll be at the forefront of verifying complex sensor subsystems, working with industry-leading methodologies like UVM and Formal Verification. You'll collaborate with architects, design teams, and software engineers to ensure the quality and reliability of our sensor technologies.
The role encompasses the entire ASIC design verification process, from test planning and environment development to coverage analysis and tapeout quality metrics. You'll be responsible for developing sophisticated testbenches, writing SystemVerilog assertions, and creating efficient verification frameworks.
We offer a comprehensive benefits package including competitive salary, stock options, performance bonuses, and extensive health coverage. Our Cork location provides an excellent quality of life, situated in Ireland's second-largest economic engine with access to international destinations through Cork airport.
The ideal candidate will bring strong technical expertise in ASIC verification, excellent problem-solving abilities, and a collaborative mindset. You'll have the opportunity to work on projects that directly impact next-generation consumer electronics and automotive applications, while growing your career in a supportive, innovation-driven environment.
Join our team and be part of developing technologies that are shaping the future of sensor-based applications across multiple industries. We provide extensive support for professional growth, including education assistance and mentorship opportunities, making this an ideal role for someone looking to advance their career in hardware verification.
Responsibilities For Sensor Subsystem Design Verification Engineer
- Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
- Developing Testbenches and Verification Components
- Test plan development based on Design documents
- Writing and debugging SystemVerilog assertions
- Analysing coverage data and working with Design teams
- Develop/augment framework for running regressions
- Running/Debugging Power aware simulations
- Support integration of design in higher-level subsystem
- Python/Perl automation for improving workflows
- Documentation
Requirements For Sensor Subsystem Design Verification Engineer
- Bachelor's degree in Science, Engineering, or related field
- ASIC design verification, UVM-based functional verification experience
- Experience with constrained-random verification environment
- Experience with System Verilog Assertions
- Extensive usage of RTL simulation tools
- UVM, System Verilog, Perl/Python shell-scripting skills
- Familiarity with C/C++
- Strong analytical and multitasking skills
- Excellent written and verbal skills
- Strong interpersonal skills and team player
Benefits For Sensor Subsystem Design Verification Engineer
- Salary, stock and performance related bonus
- Maternity/Paternity Leave
- Employee stock purchase scheme
- Matching pension scheme
- Education Assistance
- Relocation and immigration support
- Life, Medical, Income and Travel Insurance
- Subsidised memberships for physical and mental well-being
- Bicycle purchase scheme
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