ASIC Design Engineer (Sr) - Peripheral

Qualcomm is a global technology leader specializing in wireless technology, semiconductors, and mobile innovations.
Embedded
Senior Software Engineer
In-Person
4+ years of experience
Enterprise SaaS

Description For ASIC Design Engineer (Sr) - Peripheral

Qualcomm India Private Limited is seeking a Senior ASIC Design Engineer to join their Hardware Engineering team, focusing on peripheral IP design and development. This role presents an exciting opportunity to work with cutting-edge semiconductor technology at a global leader in wireless innovation.

The position requires a strong background in ASIC IP cores design, with 4-8 years of experience and a degree in Electrical Engineering. You'll be responsible for designing and implementing peripheral IP's, working with various protocols including AMBA (AXI, AHB, APB), and handling complex multi-clock designs.

As a senior engineer, you'll take on leadership responsibilities including mentoring junior engineers, managing projects independently, and collaborating with cross-functional teams. Your expertise in low-power design, timing analysis, and RTL development will be crucial for success in this role.

The role offers excellent growth opportunities within Qualcomm's innovative environment. You'll work alongside industry experts and contribute to groundbreaking semiconductor solutions. The company provides comprehensive benefits including health coverage, professional development programs, and work-life balance support.

Key technical requirements include proficiency in System Verilog, Verilog, and various ASIC development tools. Strong problem-solving abilities and excellent communication skills are essential, as you'll be interfacing with multiple teams and guiding junior engineers.

This position is ideal for someone who is passionate about semiconductor design, enjoys technical leadership, and wants to contribute to next-generation technology solutions. Join Qualcomm to be part of a team that's shaping the future of wireless technology and semiconductor innovation.

Last updated 2 months ago

Responsibilities For ASIC Design Engineer (Sr) - Peripheral

  • Design and microarchitecture solutions for peripheral IP's
  • Guide and mentor junior engineers
  • Engage with external teams to drive/resolve cross team dependencies
  • Take complete responsibility of one or more projects
  • Make schedule estimates
  • Work closely with SoC verification and validation teams

Requirements For ASIC Design Engineer (Sr) - Peripheral

Java
Python
  • 4-8 years of work experience in ASIC IP cores design
  • Bachelor's or Master's in Electrical Engineering
  • Knowledge of AMBA protocols - AXI, AHB, APB
  • Experience in Low power design
  • Experience in Multi Clock designs and Asynchronous interface
  • Experience with ASIC development tools (Lint, CDC, Design compiler, Primetime)
  • Strong experience in micro architecting RTL design
  • Excellent problem solving and communication skills
  • Experience in System Verilog, Verilog, C/C++, Perl and Python

Benefits For ASIC Design Engineer (Sr) - Peripheral

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning and future security programs
  • Emotional/mental wellbeing support
  • Work-life balance resources
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

Interested in this job?

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