ASIC Design Verification Engineer

A company of inventors that unlocked 5G, transforming industries through connectivity and world-changing technologies.
$108,000 - $177,500
Backend
Mid-Level Software Engineer
In-Person
1,000 - 5,000 Employees
3+ years of experience
Enterprise SaaS

Description For ASIC Design Verification Engineer

Qualcomm Technologies, Inc. is seeking an ASIC Design Verification Engineer to join their innovative team. This role is perfect for experienced engineers passionate about verification technologies and complex system development. The position offers a comprehensive scope of work in the verification domain, from system-level conceptualization through to post-silicon support.

The role demands expertise in advanced verification methodologies, particularly SystemVerilog-UVM, and involves working on cutting-edge technologies in the 5G space. You'll be responsible for developing comprehensive pre-silicon test plans, creating robust testbenches, and implementing assertion models for digital power IP's. The position also involves working with power-aware UPF verification flows and developing automation solutions to enhance verification efficiency.

The ideal candidate will bring at least 3 years of DV experience, strong proficiency in UVM and assertion-based verification technologies, and a solid understanding of SOC systems. Experience with caches, DDR memory protocols, and formal verification methods is crucial. The role offers exposure to multiple successful tapeouts and post-silicon debug opportunities.

Qualcomm provides an excellent environment for professional growth, offering competitive compensation including base salary, annual bonuses, and RSU grants. The company's comprehensive benefits package includes health coverage, 401k programs, educational support, and mental health resources. This position offers the opportunity to work with leading experts in the field while contributing to transformative technologies that impact global connectivity and innovation.

Last updated a day ago

Responsibilities For ASIC Design Verification Engineer

  • Complete verification lifecycle from system-level concept to tape out and post-silicon support
  • Pre-silicon test planning for digital power IP's
  • Testbench development using SystemVerilog-UVM
  • Coverage development and assertion model development
  • Formal verification (property checking)
  • Power-aware UPF verification flow and methodology
  • Develop automation to improve verification efficiency

Requirements For ASIC Design Verification Engineer

Python
  • Minimum 3 years of DV experience using uvm/assertion based verification technologies
  • Experience in verifying complex SOC or SOC subsystems
  • Experience with caches and DDR memory protocol verification
  • Experience with using memory verification VIP's
  • Bachelor's degree in Science, Engineering, or related field with 2+ years experience OR Master's degree with 1+ year experience OR PhD
  • Skill proficiency in UVM, system verilog, assertion, C++, python
  • Technology knowledge in DDR, CACHE, SOC

Benefits For ASIC Design Verification Engineer

401k
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Comprehensive health benefits
  • 401k program
  • Educational support
  • Mental health resources
  • Work-life balance programs

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