ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Technologies, Inc. is seeking an experienced ASIC Design Verification Engineer to join their innovative team in Santa Clara, CA. This role represents an exciting opportunity to work at the forefront of 5G technology and semiconductor development.

The position involves comprehensive responsibility for the complete verification lifecycle of digital power IPs, from initial system-level concept through to tape out and post-silicon support. You'll be working with advanced verification methodologies, particularly SystemVerilog-UVM, while developing test plans, coverage models, and implementing formal verification techniques.

As an ASIC Design Verification Engineer, you'll be instrumental in:

• Developing and executing comprehensive pre-silicon test plans
• Creating and maintaining testbenches using SystemVerilog-UVM
• Implementing power-aware UPF verification flows
• Developing automation solutions to enhance verification efficiency
• Contributing to post-silicon support and debugging

The ideal candidate brings at least 3 years of DV experience with a strong background in UVM/assertion-based verification technologies. Experience with SOC verification, DDR memory protocols, and successful tapeout projects is essential. Knowledge of C++ for firmware/driver development is also valuable.

Qualcomm offers an exceptional environment for professional growth, providing:

• Opportunity to work with leading engineering and technology experts
• Comprehensive benefits including world-class health coverage
• Professional development through continuous learning programs
• Tuition reimbursement and mentorship opportunities
• Collaborative, inclusive culture fostering innovation

Join Qualcomm's team of inventors and contribute to transformative technologies that are reshaping industries and enriching lives through advanced connectivity solutions. Your expertise will help drive the future of 5G technology and beyond, while working alongside some of the industry's brightest minds.

This role offers competitive compensation ranging from $108,000 to $177,500, along with additional benefits including annual bonus potential and RSU grants. The position is based in Santa Clara, CA, where you'll be part of a dynamic team pushing the boundaries of semiconductor technology.