ASIC Design Verification Engineer

Leading technology innovator that pushes boundaries to enable next-generation experiences and drives communication transformation.
$108,000 - $177,500
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
2+ years of experience
Enterprise SaaS

Description For ASIC Design Verification Engineer

Qualcomm Technologies, Inc. is seeking an ASIC Design Verification Engineer to join their innovative team. This role is crucial in pushing the boundaries of technology innovation and enabling next-generation experiences. The position involves comprehensive verification responsibilities, from system-level concept to tape out and post-silicon support.

The ideal candidate will work with advanced verification methodologies, particularly SystemVerilog-UVM, and be involved in various aspects of verification including coverage development, assertion model development, and formal verification. The role requires expertise in power-aware UPF verification flow and the ability to develop automation solutions to enhance verification efficiency.

Qualcomm offers an exceptional work environment with opportunities to work alongside leading engineering and technology experts. The company provides comprehensive benefits including competitive base salary ($108,000-$177,500), annual bonuses, RSU grants, and extensive health and wellness benefits. The position offers significant growth potential and the chance to contribute to world-changing innovations.

The role requires a minimum of 2 years of experience with ASIC design and verification tools, with preferred qualifications including expertise in digital design concepts, RTL languages, and computer architecture fundamentals. This is an excellent opportunity for someone looking to advance their career in hardware verification while working on cutting-edge technology at a global leader in the semiconductor industry.

Last updated 6 hours ago

Responsibilities For ASIC Design Verification Engineer

  • Complete verification lifecycle from system-level concept to tape out and post-silicon support
  • Pre-silicon test planning for digital power IP's
  • Testbench development using SystemVerilog-UVM
  • Coverage development and assertion model development
  • Formal verification (property checking)
  • Power-aware UPF verification flow and methodology
  • Develop automation to improve verification efficiency

Requirements For ASIC Design Verification Engineer

Python
  • Bachelor's degree in Engineering, Science, or closely related field
  • 2+ years of experience with ASIC design and verification tools, techniques, and methodology

Benefits For ASIC Design Verification Engineer

Medical Insurance
401k
Equity
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Comprehensive health benefits
  • Financial planning support
  • Emotional/mental health support
  • Wellbeing programs

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