ASIC Design Verification Engineer

A company of inventors that unlocked 5G, transforming industries through connectivity and world-changing technologies.
$153,200 - $229,800
Backend
Senior Software Engineer
In-Person
5,000+ Employees
6+ years of experience
Enterprise SaaS

Description For ASIC Design Verification Engineer

Qualcomm Technologies, Inc. is seeking an experienced ASIC Design Verification Engineer to join their innovative team. This role is crucial in developing and verifying complex SOC systems, focusing on comprehensive pre-silicon test planning and verification methodologies. The position offers an opportunity to work with cutting-edge technologies in 5G and connectivity, while being part of a team that transforms industries through technological innovation.

The ideal candidate will have extensive experience in DV using UVM/assertion-based verification technologies, with strong expertise in SOC verification, cache systems, and DDR memory protocols. You'll be responsible for the complete verification lifecycle, from initial concept to post-silicon support, utilizing advanced methodologies like SystemVerilog-UVM and formal verification techniques.

This role offers competitive compensation ranging from $153,200 to $229,800, along with comprehensive benefits including annual bonuses, RSU grants, and educational support. You'll be working with some of the industry's leading engineering experts, contributing to world-changing innovations in connectivity and mobile technologies.

The position requires a minimum of 6 years of relevant experience, with a strong background in verification technologies and SOC systems. You'll be joining a company known for its inventive culture and commitment to pushing the boundaries of what's possible in mobile and connectivity technologies. This is an excellent opportunity for someone looking to make a significant impact in the semiconductor industry while working on cutting-edge technologies that shape the future of global connectivity.

Last updated 2 months ago

Responsibilities For ASIC Design Verification Engineer

  • Complete verification lifecycle from system-level concept to tape out and post-silicon support
  • Pre-silicon test planning for digital power IP's
  • Testbench development using SystemVerilog-UVM
  • Coverage development and assertion model development
  • Formal verification (property checking)
  • Deploy power-aware UPF verification flow and methodology
  • Develop automation to improve verification efficiency

Requirements For ASIC Design Verification Engineer

Python
  • Minimum 6 years of DV experience using uvm/assertion based verification technologies
  • Experience in verifying complex SOC or SOC subsystems
  • Experience with caches and DDR memory protocol verification
  • Experience with using memory verification VIP's
  • Exposure to DDR phy
  • Exposure to firmware/driver development using c++
  • Exposure with multiple successful tapeouts from conception to post silicon debug
  • Bachelor's degree in Science, Engineering, or related field with 4+ years experience OR Master's with 3+ years OR PhD with 2+ years

Benefits For ASIC Design Verification Engineer

Medical Insurance
Education Budget
Equity
  • Annual discretionary bonus program
  • Annual RSU grants
  • Competitive benefits package
  • Medical Insurance
  • Educational support

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