ASIC Timing and Methodology Engineer

A global leader in wireless technology innovation and semiconductor manufacturing.
$140,000 - $210,000
Backend
Senior Software Engineer
In-Person
5,000+ Employees
4+ years of experience
AI · Automotive · Enterprise SaaS

Description For ASIC Timing and Methodology Engineer

Qualcomm Technologies is seeking an experienced ASIC Timing and Methodology Engineer to join their team in San Diego. This role is crucial for developing and implementing timing analysis methodologies for cutting-edge semiconductor products across Mobile, Compute, Automotive, and IOT markets. Working with state-of-the-art 5nm, 4nm, and beyond process technologies, you'll be responsible for ensuring timing closure and validation across complex SOC designs.

The position offers an opportunity to work with industry-leading tools and methodologies, collaborating with cross-functional teams including physical design, CAD, IP, and Design Technology teams. You'll be involved in comprehensive timing analysis, from Spice simulations for PVT corners to STA methodology implementation using advanced tools like PT-SI and Tempus.

This role combines technical expertise in ASIC design with strategic thinking, as you'll be responsible for improving timing convergence processes company-wide and supporting new advanced process technologies from PDK to VLSI design production. The position requires strong programming skills and offers exposure to machine learning applications in chip design.

Qualcomm provides an excellent compensation package, including competitive base salary, annual bonuses, RSU grants, and comprehensive benefits. The company's culture promotes innovation, continuous learning, and professional growth through mentorship programs and tuition reimbursement. Working at Qualcomm means being at the forefront of semiconductor technology and contributing to products that impact millions of users worldwide.

The ideal candidate will bring a strong foundation in ASIC design, excellent problem-solving abilities, and the desire to work in a collaborative, fast-paced environment. This role offers the opportunity to shape the future of semiconductor technology while working with some of the industry's brightest minds.

Last updated 13 days ago

Responsibilities For ASIC Timing and Methodology Engineer

  • Perform timing analysis for Mobile, Compute, Automotive and IOT markets
  • Work with physical design team on timing closure
  • Collaborate with CAD teams, IP teams and Design Technology Teams
  • Validate PVT corners and STA vs spice correlation
  • Drive STA methodology using PT-SI, Tempus and timing ECO tools
  • Support timing sign off for complex SOCs
  • Improve timing convergence process across the company

Requirements For ASIC Timing and Methodology Engineer

Python
Java
Linux
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design experience
  • Experience with timing analysis and STA methodology
  • Knowledge of Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim)
  • Understanding of RTL to GDS digital flow
  • Programming skills in Python, Perl, TCL, Unix shell, C/C++
  • Experience with PT/PT-SI and Tempus tools
  • Knowledge of timing constraints and analysis

Benefits For ASIC Timing and Methodology Engineer

Medical Insurance
401k
Vision Insurance
Dental Insurance
Mental Health Assistance
Equity
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Comprehensive health coverage
  • Financial planning and retirement benefits
  • Mental health and wellbeing support
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship programs

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