ASIC Timing and Methodology Engineer
Description For ASIC Timing and Methodology Engineer
Qualcomm Technologies, Inc. is seeking an experienced ASIC Timing and Methodology Engineer to join their team. This role focuses on critical timing analysis for cutting-edge technologies in Mobile, Compute, Automotive, and IOT markets. Working with state-of-the-art methodologies and tools in advanced process technologies (5nm, 4nm and beyond), you'll be responsible for ensuring timing closure and validation across complex SOC designs. The position offers exposure to advanced semiconductor development, collaboration with multiple engineering teams, and the opportunity to work on innovative solutions. The role combines technical expertise in timing analysis with strategic methodology development, making it ideal for engineers passionate about pushing the boundaries of semiconductor technology. Qualcomm offers competitive compensation, including base salary, bonuses, and equity grants, along with comprehensive benefits and professional development opportunities. The company's innovative culture and global impact make it an excellent choice for career growth in semiconductor engineering.
Responsibilities For ASIC Timing and Methodology Engineer
- Perform timing analysis for Mobile, Compute, Automotive and IOT markets
- Work with physical design teams on timing closure
- Validate timing packages across advanced process technologies
- Drive STA methodology using PT-SI, Tempus and timing ECO tools
- Support timing sign off for complex SOCs
- Conduct Spice simulations for PVT corners validation
- Improve timing convergence process across the company
Requirements For ASIC Timing and Methodology Engineer
- Bachelor's degree in Science, Engineering, or related field with 4+ years experience, or Master's with 3+ years, or PhD with 2+ years
- Experience with timing analysis and STA tools (PT/PT-SI, Tempus)
- Knowledge of Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim)
- Understanding of RTL to GDS digital flow
- Programming skills in Python, Perl, TCL, Unix shell, C/C++
- Experience with timing closure and validation
Benefits For ASIC Timing and Methodology Engineer
- Annual discretionary bonus program
- Annual RSU grants
- Competitive benefits package
- Medical coverage for employees and dependents
- Financial planning resources
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