ASICS Design Verification Engineer (Santa Clara, CA)

Qualcomm is a company of inventors that unlocked 5G, transforming industries and creating jobs through connectivity innovation.
$153,200 - $229,800
Backend
Senior Software Engineer
In-Person
5,000+ Employees
4+ years of experience
AI

Description For ASICS Design Verification Engineer (Santa Clara, CA)

Qualcomm Technologies, Inc. is seeking an experienced ASICS Design Verification Engineer to join their team in Santa Clara, CA. This role represents an exciting opportunity to work with a company at the forefront of 5G technology and connectivity innovation.

The position involves comprehensive responsibility for the complete verification lifecycle, from system-level concept through to tape out and post-silicon support. As a Design Verification Engineer, you'll be instrumental in developing and implementing verification strategies for digital power IP's using advanced methodologies including SystemVerilog-UVM.

Key responsibilities include pre-silicon test planning, testbench development, coverage development, and assertion model development. You'll also be working with power-aware UPF verification flow and methodology, while developing automation solutions to enhance verification efficiency.

The ideal candidate brings strong experience in UVM/assertion-based verification technologies, complex SOC verification, and memory protocol verification. Experience with DDR phy, firmware development using C++, and successful tapeout experience are valuable assets.

Qualcomm offers a competitive compensation package ranging from $153,200 to $229,800, along with comprehensive benefits including medical, dental, and vision insurance, 401k, equity opportunities, and education budget. The company's commitment to innovation and technological advancement makes it an ideal environment for professional growth in the semiconductor industry.

Working at Qualcomm means joining a team of inventors and innovators who are shaping the future of connectivity. The company's culture promotes collaboration, creativity, and continuous learning, with access to cutting-edge technology and the opportunity to work on projects that have global impact.

This role requires a Bachelor's degree in Science, Engineering, or related field with 4+ years of relevant experience, or equivalent combinations of education and experience. The position is based in Santa Clara, CA, offering the opportunity to work in one of the world's leading tech hubs.

Join Qualcomm to be part of a team that's driving the future of technology while working on challenging and rewarding projects in ASIC design verification.

Last updated 2 days ago

Responsibilities For ASICS Design Verification Engineer (Santa Clara, CA)

  • Complete verification lifecycle from system-level concept to tape out
  • Pre-silicon test planning for digital power IP's
  • Testbench development using SystemVerilog-UVM
  • Coverage development
  • Assertion model development and formal verification
  • Deploy power-aware UPF verification flow and methodology
  • Develop automation to improve verification efficiency

Requirements For ASICS Design Verification Engineer (Santa Clara, CA)

Java
Python
  • DV experience using uvm/assertion based verification technologies
  • Experience in verifying complex SOC or SOC subsystems
  • Experience with caches and DDR memory protocol verification
  • Experience with using memory verification VIP's
  • Exposure to DDR phy
  • Exposure to firmware/driver development using c++
  • Exposure with multiple succesfull tapeouts from conception to post silicon debug
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of experience

Benefits For ASICS Design Verification Engineer (Santa Clara, CA)

Medical Insurance
Dental Insurance
Vision Insurance
401k
Equity
Education Budget
  • Medical Insurance
  • Dental Insurance
  • Vision Insurance
  • 401k
  • Equity
  • Education Budget

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