CPU Floorplan and Integration Engineer

Leading technology company developing high-performance, energy-efficient server solutions for data center applications.
$198,700 - $298,100
Backend
Staff Software Engineer
In-Person
5,000+ Employees
5+ years of experience
Enterprise SaaS

Description For CPU Floorplan and Integration Engineer

Qualcomm Technologies is seeking a CPU Floorplan and Integration Engineer to join their Data Center team in developing cutting-edge server solutions. This role is crucial in transforming the industry through next-generation computing platforms. As part of the team, you'll collaborate with world-class engineers to create innovative solutions that push the boundaries of performance and energy efficiency.

The position involves working closely with microarchitecture, RTL design, and physical design teams to design, floorplan, and integrate CPU designs that meet aggressive power, area, and performance goals. You'll be responsible for managing chip-level implementations, overseeing full chip floorplan, and ensuring designs meet all technical requirements.

The ideal candidate will bring extensive experience in physical design and integration, with a strong background in electrical engineering. You'll need expertise in synthesis, place and route, and signoff timing/power analysis, along with deep knowledge of low power and high-performance design methodologies.

Qualcomm offers a comprehensive benefits package including competitive base salary, annual bonuses, RSU grants, and extensive health coverage. The company fosters a culture of innovation and continuous learning, providing opportunities for professional growth through mentorship programs and tuition reimbursement.

This role presents an exceptional opportunity to work on server-class high-performance CPU solutions while collaborating with industry-leading experts in silicon development. Join Qualcomm to be part of transformative technology development that shapes the future of data center computing.

Last updated 22 days ago

Responsibilities For CPU Floorplan and Integration Engineer

  • Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP integration
  • Oversee full chip floorplan, area optimizations, block partitioning, and pin assignments
  • Manage chip-level place and route, and finalize the CPU database
  • Coordinate custom layout integration
  • Collaborate with external teams for IP requirements
  • Develop workflows for chip integration and analysis
  • Ensure designs are validated for functional and electrical robustness

Requirements For CPU Floorplan and Integration Engineer

  • Bachelor's degree or higher in Electrical Engineering with over 5 years of practical experience
  • Proficiency in synthesis, place and route, and signoff timing/power analysis
  • Expertise in block-level implementation and full chip floorplanning
  • Skilled in physical design, integration, and verification of large processor designs
  • Strong understanding of circuit and layout design principles
  • In-depth understanding of extraction, static timing analysis, and EMIR flows
  • Experience in deep submicron process technology nodes

Benefits For CPU Floorplan and Integration Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
401k
Equity
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Medical coverage for employees and dependents
  • Financial planning assistance
  • Mental health and wellbeing support
  • Tuition reimbursement
  • Mentorship programs

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