CPU Physical Design Timing Engineer

Join Qualcomm Technologies, Inc. as a CPU Physical Design Timing Engineer and be part of reimagining silicon and creating transformative computing platforms. In this role, you'll work on defining, developing, and driving CPU timing closure for Oryon CPU Cores, collaborating with microarchitecture and RTL design teams to meet aggressive power, area, and performance goals.

You'll be responsible for STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs, working with industry-standard tools like PT/Tempus. The position offers opportunities to work on industry-leading technology nodes N2/N3 and collaborate with Qualcomm's central timing technology & methodology team.

The role requires strong expertise in STA timing analysis, AOCV/POCV concepts, and scripting languages (TCL/Perl/Python). You'll be working in a cross-collaborative environment with some of the most talented engineers in the world, creating designs that push the envelope on performance and energy efficiency.

Qualcomm offers a competitive compensation package ranging from $139,000 to $208,000, plus annual bonuses and RSU grants. The company provides comprehensive benefits including health coverage, 401k, education support, and mentorship programs. This position offers significant professional growth opportunities while working on cutting-edge technology in a supportive, inclusive culture.

The ideal candidate will have at least 4 years of relevant experience with a Bachelor's degree (or equivalent combination of education and experience), strong technical writing and communication skills, and in-depth knowledge of digital flow design implementation from RTL to GDS.