CPU Physical Design Timing Engineer

NUVIA, now part of Qualcomm, focuses on reimagining silicon and creating computing platforms to transform the industry.
Austin, TX, USAFolsom, CA, USA
$148,300 - $222,500
Backend
Senior Software Engineer
In-Person
4+ years of experience
Enterprise SaaS

Description For CPU Physical Design Timing Engineer

Join Qualcomm Technologies, Inc. as a CPU Physical Design Timing Engineer working on cutting-edge Oryon CPU Cores. This role offers an exciting opportunity to work with industry-leading technology at NUVIA, now part of Qualcomm. You'll be responsible for defining, developing, and driving CPU timing closure, working alongside talented engineers to push the boundaries of performance and energy efficiency. The position involves sophisticated timing analysis, constraint development, and collaboration with microarchitecture and RTL teams. You'll work with state-of-the-art tools and technologies, including industry-standard STA tools like Primetime and Tempus. The role offers excellent growth opportunities, working on advanced technology nodes N2/N3, and the chance to impact multiple CPU projects through timing infrastructure and methodology development. The compensation is competitive, ranging from $148,300 to $222,500, complemented by comprehensive benefits including bonuses and RSU grants. This is an ideal opportunity for experienced engineers passionate about CPU design and timing optimization.

Last updated 4 hours ago

Responsibilities For CPU Physical Design Timing Engineer

  • Define, develop and drive CPU timing closure for Oryon CPU Cores
  • STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs
  • Timing analysis, validation and debug across multiple PVT conditions
  • Run Primetime and/or Tempus for STA flow optimization
  • Find root cause of timing miscorrelation and propose solutions
  • Work on automation scripts within STA/PD tools
  • Evaluate multiple timing methodologies/tools

Requirements For CPU Physical Design Timing Engineer

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years experience
  • Strong expertise in STA timing analysis basics, AOCV/POCV concepts
  • Hands-on experience with STA tools - Prime-time, Tempus
  • Expert in scripting languages – TCL, Perl, Python
  • Knowledge of ASIC back-end design flows and methods
  • Basic knowledge of device physics

Benefits For CPU Physical Design Timing Engineer

Medical Insurance
Education Budget
Equity
  • Annual discretionary bonus program
  • Annual RSU grants
  • Competitive benefits package
  • Medical coverage
  • Education assistance

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