CPU RTL Power management Design Engineer-Sr Staff Engineer

A leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation.
$150,000 - $250,000
Backend
Staff Software Engineer
In-Person
5,000+ Employees
12+ years of experience
AI · Hardware

Description For CPU RTL Power management Design Engineer-Sr Staff Engineer

Qualcomm is seeking a talented CPU RTL Power management Design Engineer at the Sr Staff Engineer level to join our team. This role focuses on developing and optimizing power management solutions for high-performance, low-power devices. The position involves working closely with chip architects to conceive micro-architecture and contribute to product definition through early involvement in the product lifecycle.

As a key member of our team, you'll be responsible for performance exploration, microarchitecture development, RTL design, and working with multi-functional engineering teams. Your expertise in power management, including DVFS, idle power management, and clock management, will be crucial in delivering efficient solutions.

The ideal candidate will bring strong technical skills in Verilog/VHDL, logic design principles, and a deep understanding of CPU microarchitecture. With your MS degree in Computer or Electrical Engineering and extensive experience in the field, you'll contribute to pushing the boundaries of what's possible in CPU design.

At Qualcomm, you'll work alongside leading engineering and technology experts, with access to continuous learning opportunities, tuition reimbursement, and mentorship programs. We offer comprehensive benefits including world-class health coverage, financial planning support, and resources for emotional and mental wellbeing.

Join us in creating next-generation technologies that transform how the world connects, computes, and communicates. Your work will directly impact the future of mobile and computing technology, making this an exciting opportunity for those passionate about innovation and technical excellence.

Last updated 2 months ago

Responsibilities For CPU RTL Power management Design Engineer-Sr Staff Engineer

  • Performance exploration with CPU modeling team
  • Microarchitecture development and specification
  • RTL ownership and development
  • Functional verification support
  • Performance verification support
  • Design delivery and implementation

Requirements For CPU RTL Power management Design Engineer-Sr Staff Engineer

Python
  • Thorough knowledge of microprocessor architecture
  • Expertise in power management (DVFS), idle power management, and clock management
  • Knowledge of Verilog and/or VHDL
  • Knowledge of logic design principles
  • MS degree in Computer or Electrical Engineering
  • Understanding of low power microarchitecture techniques
  • Understanding of high-performance CPU microarchitecture
  • Experience with scripting languages like Perl or Python

Benefits For CPU RTL Power management Design Engineer-Sr Staff Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning and future security programs
  • Emotional and mental wellbeing support
  • Work-life balance resources
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

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