CPU STA/Timing Engineer (Staff level)
Description For CPU STA/Timing Engineer (Staff level)
Qualcomm India Private Limited is seeking a Staff-level CPU STA/Timing Engineer to join their Hardware Engineering team in Hyderabad. This role combines advanced technical expertise in ASIC design with a focus on timing and power optimization. The ideal candidate will bring 5+ years of relevant experience in high-speed CPU implementation, working with cutting-edge tools and methodologies.
The position offers an opportunity to work on complex CPU architectures, implementing sophisticated timing and power solutions. You'll be responsible for complete ASIC flow optimization, constraint management, and formal verification processes. The role requires expertise in various tools including Primetime, Tempus, and proficiency in programming languages like Python, Perl/Tcl, and C++.
Qualcomm provides a comprehensive benefits package including world-class health coverage, financial planning support, and continuous learning opportunities. The company fosters an inclusive culture that encourages innovation and professional growth. This role offers the chance to work alongside leading engineering experts while contributing to breakthrough technologies that impact global wireless communication.
The position demands strong problem-solving abilities and deep technical knowledge in ASIC development and debugging. You'll be part of a team that pushes the boundaries of CPU architecture and implementation, working on critical timing paths and power optimization challenges. This is an excellent opportunity for a seasoned engineer looking to advance their career at a company that's at the forefront of semiconductor and mobile technology innovation.
Responsibilities For CPU STA/Timing Engineer (Staff level)
- Complete ASIC flow with low power, performance and area optimization
- Implement and optimize power domain with complex UPF/CPF definition
- Perform formal verification using Formality/Conformal
- Implement low power techniques
- Handle high speed CPU implementation
- Manage Clock Tree Implementation for High Speed Design
- Work on constraint management and Verilog coding
Requirements For CPU STA/Timing Engineer (Staff level)
- Bachelor's/Master's/PhD in Computer Science, Electrical/Electronics Engineering or related field
- Extensive experience in Place & Route with FC or Innovus
- Experience with STA using Primetime and/or Tempus
- Proficient in constraint generation and validation
- Experience with multiple power domain implementation
- Formal verification experience
- Perl/Tcl, Python, C++ skills
- Strong problem solving and ASIC development/debugging skills
- Experience with CPU micro-architecture
- Clock Tree Implementation experience
- Verilog coding experience
Benefits For CPU STA/Timing Engineer (Staff level)
- World-class health coverage for employees and eligible dependents
- Financial planning and future preparation programs
- Emotional/mental strength and resilience support
- Wellbeing programs and resources
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
