CPU STA/Timing Engineer - Staff/Sr. Staff

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Description For CPU STA/Timing Engineer - Staff/Sr. Staff

Qualcomm, a leading technology innovator, is seeking a CPU STA/Timing Engineer at the Staff/Sr. Staff level to join their Hardware Engineering team in Bangalore. This role focuses on critical timing analysis and optimization for complex SOC designs. The position requires expertise in timing flows, multi-clock domain designs, and deep submicron process technology. You'll collaborate with cross-functional teams including RTL design, DFT, and physical design to ensure successful timing closure.

The ideal candidate will have extensive experience with STA on large SOC designs, strong knowledge of library cells and optimizations, and excellent communication skills. This role offers an opportunity to work on cutting-edge technology with industry leaders while contributing to next-generation hardware solutions. Qualcomm provides comprehensive benefits including world-class health coverage, professional development opportunities, and wellbeing programs.

As part of Qualcomm's hardware engineering team, you'll be at the forefront of innovation, working on projects that push the boundaries of what's possible in digital transformation. The company's supportive, inclusive culture encourages collaboration and professional growth, making it an ideal environment for experienced engineers looking to advance their careers in hardware design and timing analysis.

Last updated 2 days ago

Responsibilities For CPU STA/Timing Engineer - Staff/Sr. Staff

  • Work with design and DFT teams to understand, implement and validate constraints
  • Run SOC timing runs at all hierarchies
  • Analyze timing and work with RTL/DFT teams to facilitate logic changes
  • Feedback to block level and top level physical design engineers
  • Work with CAD team to implement timing infrastructure
  • Create ECOs from timing runs to help timing closure
  • Document and help with timing methodology definition

Requirements For CPU STA/Timing Engineer - Staff/Sr. Staff

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field with 4+ years experience
  • Experience in timing flows with industry standard tools
  • Experience in all aspects of timing closure for multi-clock domain designs
  • Experience in deep submicron process technology nodes
  • Experience with STA on large SOC with multi-scenario timing closure
  • Knowledge of library cells and optimizations
  • Solid understanding industry standard tools for synthesis
  • Good communication skills
  • Knowledge of basic SoC architecture and HDL languages like Verilog

Benefits For CPU STA/Timing Engineer - Staff/Sr. Staff

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and eligible dependents
  • Financial planning and future preparation programs
  • Emotional/mental strength and resilience support
  • Wellbeing programs
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

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