CPU STA/Timing Engineer - Staff/Sr. Staff
Description For CPU STA/Timing Engineer - Staff/Sr. Staff
Qualcomm, a leading technology innovator, is seeking a CPU STA/Timing Engineer at the Staff/Sr. Staff level to join their team in Bangalore. This role is crucial for the development of next-generation hardware solutions, focusing on timing analysis and optimization for complex SOC designs.
The position requires a deep understanding of hardware engineering principles and timing closure methodologies. You'll be working with cutting-edge technology, collaborating with cross-functional teams including RTL design, DFT, and physical design teams to ensure optimal timing performance of sophisticated hardware systems.
As a Staff Engineer, you'll be responsible for running and analyzing SOC timing, implementing constraints, and driving timing closure across multiple hierarchies. The role demands expertise in industry-standard tools, deep submicron process technology, and multi-scenario timing closure techniques.
Qualcomm offers an exceptional environment for professional growth, providing access to leading engineering experts and opportunities to work on breakthrough technologies. The company provides comprehensive benefits including world-class health coverage, financial planning support, and wellbeing programs.
The ideal candidate will have an MS in Electrical Engineering with 10 years of practical experience, demonstrating expertise in timing flows, multi-clock domain designs, and STA methodologies. Strong communication skills and the ability to work effectively with cross-functional teams are essential.
Join Qualcomm to be part of a team that's pushing the boundaries of what's possible in hardware engineering, while enjoying opportunities for continuous learning, mentorship, and career advancement in a supportive, inclusive culture.
Responsibilities For CPU STA/Timing Engineer - Staff/Sr. Staff
- Work with design and DFT teams to understand, implement and validate constraints
- Run SOC timing runs at all hierarchies
- Analyze timing and work with RTL/DFT teams to facilitate logic changes
- Feedback to block level and top level physical design engineers
- Work with CAD team to implement timing infrastructure
- Create ECOs from timing runs to help timing closure
- Document and help with timing methodology definition
Requirements For CPU STA/Timing Engineer - Staff/Sr. Staff
- MS degree in Electrical Engineering with 10 years practical experience
- Experience in timing flows with industry standard tools
- Experience in all aspects of timing closure for multi-clock domain designs
- Experience in deep submicron process technology nodes
- Experience with STA on large SOC with multi-scenario timing closure
- Knowledge of library cells and optimizations
- Solid understanding of industry standard tools for synthesis
- Good communication skills
- Knowledge of basic SoC architecture and HDL languages like Verilog
Benefits For CPU STA/Timing Engineer - Staff/Sr. Staff
- World-class health coverage for employees and dependents
- Financial planning and future security programs
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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