CPU STA/Timing Engineer - Staff/Sr. Staff
Description For CPU STA/Timing Engineer - Staff/Sr. Staff
Qualcomm is seeking a CPU STA/Timing Engineer at the Staff/Sr. Staff level to join our Hardware Engineering team in Bangalore. As a leading technology innovator, we're looking for talented individuals to help push the boundaries of what's possible in next-generation experiences.
The role focuses on critical timing analysis and optimization for complex SOC designs. You'll work closely with microarchitecture, RTL design, CAD, and physical design teams to ensure successful timing closure across all hierarchies. Your responsibilities will include implementing and validating timing constraints, running comprehensive SOC timing analysis, and driving timing closure through detailed analysis and optimization.
The ideal candidate brings 10 years of practical experience in timing analysis, with deep expertise in multi-clock domain designs and submicron process technologies. You should have strong knowledge of industry-standard tools for synthesis, place & route, and timing analysis. Experience with STA on large SOCs and timing ECO techniques is essential.
At Qualcomm, you'll join a collaborative environment where your ideas contribute to world-changing innovations. We offer comprehensive benefits including health coverage, financial planning support, continuous learning opportunities, and wellbeing programs. You'll work alongside leading engineering experts while having access to mentorship and professional development resources.
This role offers the opportunity to work on cutting-edge technology while solving complex challenges that impact global communications. If you're passionate about pushing technical boundaries and want to grow your career with an industry leader, we encourage you to apply.
Responsibilities For CPU STA/Timing Engineer - Staff/Sr. Staff
- Work with design and DFT teams to understand, implement and validate constraints
- Run SOC timing runs at all hierarchies
- Analyze timing and work with RTL/DFT teams to facilitate logic changes required
- Feedback to block level and top level physical design engineers on key fixes required for timing closure
- Work with CAD team to implement timing infrastructure
- Create ECOs from timing runs to help timing closure
- Document and help with timing methodology definition
Requirements For CPU STA/Timing Engineer - Staff/Sr. Staff
- MS degree in Electrical Engineering with 10 years of practical experience
- Experience in timing flows with industry standard tools
- Experience in all aspects of timing closure for multi-clock domain designs
- Experience in deep submicron process technology nodes
- Experience with STA on large SOC with multi-scenario timing closure
- Experience with Timing ECO techniques and implementation
- Knowledge of library cells and optimizations
- Familiar with circuit modeling, transistor fundamentals and worst case corner selection
- Solid understanding industry standard tools for synthesis, place & route and tapeout flows
- Good communication skills
- Knowledge of all aspects of timing including noise, cross-talk and others
- Knowledge of basic SoC architecture and HDL languages like Verilog
Benefits For CPU STA/Timing Engineer - Staff/Sr. Staff
- World-class health coverage for employees and dependents
- Financial planning and security programs
- Emotional/mental health support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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