Design Technology Co-Optimization (DTCO) and Power Performance Area (PPA) Scaling Engineer

Qualcomm Technologies, Inc., one of the world's leading fabless semiconductor companies, is seeking a Design Technology Co-Optimization (DTCO) and Power Performance Area (PPA) Scaling Engineer. This role is part of the core-DTCO team, focusing on pathfinding and validation of standard-cell and block-level DTCO boosters for advanced transistor architectures. The position offers a unique opportunity to work at the cutting edge of semiconductor technology, collaborating with foundry and research partners to optimize technology features for better power and performance outcomes.

The role combines deep technical expertise in semiconductor design with strategic technology optimization. You'll be responsible for evaluating advanced logic technology, conducting complex PPA analysis, and working closely with cross-functional teams to drive innovation in semiconductor design. The position requires strong analytical skills, programming proficiency, and the ability to work effectively with both internal teams and external partners.

Qualcomm offers an exceptional compensation package, including competitive base salary, annual bonuses, and RSU grants. The company provides comprehensive benefits and supports professional growth through continuous learning opportunities. This role presents an excellent opportunity for experienced engineers looking to impact the future of semiconductor technology while working with industry-leading experts in a collaborative environment.

The ideal candidate will thrive in a fast-paced R&D environment, possess strong technical skills, and have the ability to bridge the gap between design and technology optimization. This position offers the chance to work on cutting-edge technology while contributing to Qualcomm's leadership in semiconductor innovation.