DFT CAD Sr Lead Engineer

A leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation.
Backend
Staff Software Engineer
In-Person
5,000+ Employees
4+ years of experience
AI · Enterprise SaaS

Description For DFT CAD Sr Lead Engineer

Qualcomm is seeking a DFT/ATPG Methodology development lead to join their Global CAD Organization. This role focuses on developing DFTCAD methodologies for Qualcomm's 5G products in advanced FinFET semiconductor process nodes. As a key member of a global technical team, you'll collaborate with SOC Design, DFT, Product and Test, and Diagnostics teams, as well as EDA Tool vendors to develop world-class DFT methodology solutions.

The position requires a strong background in VLSI EDA/CAD methodology development, particularly in DFT and Scan/ATPG areas. You'll be responsible for leading ATPG flow development, driving new methodologies, and optimizing test quality while reducing costs. The ideal candidate should have 4-6 years of relevant experience and strong technical skills in Python and TCL.

At Qualcomm, you'll work alongside leading engineering and technology experts in the industry, contributing to world-changing innovations and breakthrough technologies. The company offers comprehensive benefits including world-class health coverage, financial planning support, mental health resources, and continuous learning opportunities.

This role offers significant growth potential within a company that's at the forefront of 5G technology and semiconductor innovation. You'll be part of a diverse, inclusive culture that values collaboration and innovation, while working on cutting-edge projects that impact global technology advancement.

Last updated 3 months ago

Responsibilities For DFT CAD Sr Lead Engineer

  • Lead DFT ATPG flow development, integration, and deployment efforts independently
  • Drive new ATPG methodology, new tool evaluation, design DoEs
  • Develop optimized recipes for improving test quality, reducing test cost, DFT cycle time, pattern simulation runtimes

Requirements For DFT CAD Sr Lead Engineer

Python
Linux
  • BE/B.Tech, ME/MTech/MS in Electrical/Electronics/Computer science Engineering
  • 4-6 years demonstrated experience in VLSI EDA/CAD methodology development in areas of DFT, Scan/ATPG
  • Strong knowledge of DFT domain specifically on Scan, ATPG and ATPG pattern simulations
  • Strong development skills in TCL, Python
  • Good understanding of SOC DFT Flow, ATE Flow and practices
  • Familiarity with standard software development process
  • Ability to plan and execute formal projects
  • Must be a team player with attention to details

Benefits For DFT CAD Sr Lead Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning and security programs
  • Mental health and emotional support
  • Wellbeing programs and resources
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

Interested in this job?

Jobs Related To Qualcomm DFT CAD Sr Lead Engineer

Lead Physical Design Engineer

Lead Physical Design Engineer position at Qualcomm India, focusing on PNR implementation and hardware engineering with comprehensive benefits and growth opportunities.

Physical Design Engineer - Staff

Staff Physical Design Engineer position at Qualcomm Technologies focusing on ASIC design and implementation of complex chip solutions.

Staff SOC Design Verification Engineer

Staff SOC Design Verification Engineer position at Qualcomm India, focusing on electronic systems verification and testing with 8+ years experience required.

Lead Physical Design Engineer

Lead Physical Design Engineer position at Qualcomm India, focusing on PNR implementation and hardware engineering with 5+ years experience required.

IC Package Layout Engineer, Up to Senior Staff

IC Package Layout Engineer position at Qualcomm focusing on advanced package design, optimization, and implementation of physical designs for semiconductor technology.