Taro Logo

Digital Design Engineer for Power Management ASICs

Leading technology innovator that pushes boundaries to enable next-generation experiences and drives communication and data processing transformation.
Embedded
Mid-Level Software Engineer
In-Person
3+ years of experience
AI · Enterprise SaaS
This job posting may no longer be active. You may be interested in these related jobs instead:

Description For Digital Design Engineer for Power Management ASICs

Qualcomm is seeking a Digital Design Engineer for Power Management ASICs to join their innovative team. This role focuses on developing Mixed-Signals IPs, ASICs, and Chipsets used in Qualcomm Snapdragon power solutions. The position involves working with international teams across all development stages, from system definition to high-volume OEM launches.

The ideal candidate will be responsible for designing state-of-the-art Mixed-Signals ASICs in advanced digital deep sub-micron CMOS processes for multi-function mobile platforms. Key responsibilities include micro-architecture design, system specification execution, and front-end design activities from architecture definition to timing closure.

At Qualcomm, you'll work alongside leading engineering and technology experts, contributing to world-changing innovations in power management solutions. The company offers comprehensive professional development opportunities, including continuous learning programs, tuition reimbursement, and mentorship opportunities.

The role requires strong technical expertise in digital design principles and experience with front-end digital design tools. You'll be part of a team that pushes the boundaries of what's possible in power management technology, working on projects that impact millions of devices worldwide.

Join Qualcomm to be part of a company that values innovation, collaboration, and professional growth. You'll have access to world-class benefits, including comprehensive health coverage, financial planning support, and wellbeing programs, all while working on cutting-edge technology that shapes the future of mobile computing.

Last updated 7 months ago

Responsibilities For Digital Design Engineer for Power Management ASICs

  • Participate in or lead design of state-of-the-art Mixed-Signals ASICs
  • Micro-architecture of chipset, chip and IP-level designs
  • Execute System specification and requirements
  • Front-end design from Architecture definition/RTL development/Simulation/Synthesis/DFT Insertion
  • Document ASIC development and hold detailed design reviews
  • Generate and maintain design schedules

Requirements For Digital Design Engineer for Power Management ASICs

Java
Linux
  • Bachelor's degree in Science, Engineering, or related field
  • 3+ years ASIC design, verification, or related work experience
  • Sound digital design principles
  • Experience with Front-end Digital design tools – HDL, RTL Linting, CDC, Synthesis, BIST/SCAN insertion, STA
  • Strong communication and organizational skills
  • Strong process-oriented mindset

Benefits For Digital Design Engineer for Power Management ASICs

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning and future security programs
  • Emotional/mental health support
  • Wellbeing programs and resources
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

Interested in this job?