Digital Verification Engineer for Power Management ASICs
Description For Digital Verification Engineer for Power Management ASICs
Qualcomm is seeking a Digital Verification Engineer to join their Power Management ASICs team. This role focuses on verifying mixed-signals IPs, ASICs, and chipsets used in Qualcomm Snapdragon power solutions. The position involves working with cutting-edge technologies including telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power solutions, and high-efficiency power management systems.
As a Digital Verification Engineer, you'll be instrumental in ensuring the quality and reliability of complex power management systems. You'll work alongside international teams throughout the entire development lifecycle, from initial system definition to high-volume OEM launches reaching over 100M+ units. The role requires expertise in UVM-compliant test-bench architecture, constrained-random stimulus creation, and comprehensive verification processes.
Qualcomm offers an exceptional environment for professional growth, providing access to leading engineering experts and breakthrough technologies. The company maintains a strong focus on innovation, particularly in 5G and AI technologies, while fostering a collaborative and inclusive culture. They offer comprehensive benefits including health coverage, professional development opportunities, and wellbeing programs.
This position is ideal for someone with strong technical skills in ASIC verification and a passion for working on cutting-edge power management solutions. You'll be part of a dynamic team that pushes the boundaries of what's possible in mobile and IoT power solutions, contributing to products that impact millions of users worldwide.
Responsibilities For Digital Verification Engineer for Power Management ASICs
- Partner with international teams in all stages of development from system definition to high-volume OEM launches
- Perform test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation
- Handle verification of digital and mixed-signals IPs
- Debug complex embedded systems including SOCs, firmware, embedded sequencers
- Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target
Requirements For Digital Verification Engineer for Power Management ASICs
- Bachelor's degree in Science, Engineering, or related field
- 3+ years ASIC design, verification, or related work experience
- Expert-level System Verilog Programming
- Advanced UVM/SV (Universal Verification Methodology using System Verilog)
- Python or Perl scripting
- Strong troubleshooting skills across embedded systems disciplines
- Strong communication and organizational skills
- Strong process-oriented mindset
Benefits For Digital Verification Engineer for Power Management ASICs
- World-class health coverage for employees and eligible dependents
- Financial planning and future preparation programs
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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