DSP / NPU Design Verification Sr lead Engineer

One of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and IP royalties.
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AI · Automotive

Description For DSP / NPU Design Verification Sr lead Engineer

Qualcomm is seeking a Senior Lead Engineer for DSP/NPU Design Verification to join their team in Bangalore. This role is crucial for delivering high-performance DSP/NPU cores that power Qualcomm's multi-tier SoC roadmap for mobile, AI, and automotive applications. The position requires 5-8 years of experience in design verification of complex proprietary DSP/NPU IP.

The role involves working with a global DSP design team on architecture, implementation, power, post-silicon, and back-end aspects. You'll be responsible for implementing System Verilog/UVM testbench architecture, developing verification methodologies, and ensuring high-quality commercial success of products. Daily tasks include working with assertions, simulation, formal verification, HW-SW co-verification, and simulation acceleration.

As a senior lead, you'll drive design verification initiatives, develop test plans, and architect verification environments. The position requires expertise in System Verilog, processor architecture, and power-aware verification. Experience with C-based testcases, UPF, and formal verification techniques is highly valued.

Qualcomm offers comprehensive benefits including world-class health coverage, financial planning support, and professional development opportunities. The company's culture promotes innovation and collaboration, working alongside leading engineering experts in the semiconductor industry. This role presents an opportunity to work on cutting-edge technology that impacts global markets while developing your career at one of the world's largest fabless semiconductor companies.

Last updated 2 hours ago

Responsibilities For DSP / NPU Design Verification Sr lead Engineer

  • Drive design verification of DSP IP by working with global DSP design team
  • Implement and improve System Verilog/UVM Testbench Architecture
  • Develop and deploy new verification methodologies and automation
  • Develop test plans and verification environments
  • Debug IP level, Subsystem and SoC level fails and bugs
  • Perform gate level simulation and verification
  • Handle power aware RTL verification

Requirements For DSP / NPU Design Verification Sr lead Engineer

Python
Linux
  • 5-8 years experience in processor/ASIC design verification
  • Solid background in Digital Design, Processor Architecture and Power aware verification
  • Expertise in System Verilog Testbench Architecture
  • Experience in C based and assembly level testcases
  • Knowledge of power aware implementation and UPF
  • Experience with formal verification and assertions
  • Proficiency in scripting (Perl, Python, Shell)
  • Strong analytical and debugging skills
  • Bachelor's/Master's degree in Computer Science, Electrical/Electronics Engineering or related field
  • Excellent interpersonal and communication skills

Benefits For DSP / NPU Design Verification Sr lead Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning and future security programs
  • Mental health and emotional wellbeing support
  • Work-life balance resources
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship programs

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