Functional DV ( Clock/Power) Verification Staff Engineer
Description For Functional DV ( Clock/Power) Verification Staff Engineer
Qualcomm Graphics HW team in Bangalore is seeking a Staff Engineer for their GPU solutions development. This role focuses on verifying Clock and power management modules, requiring expertise in GPU power and clock domains. The position demands strong verification skills, including System Verilog/UVM, and experience with low power design techniques. The ideal candidate will collaborate with global teams, owning end-to-end DV tasks from test bench coding to coverage goals.
The role offers significant growth opportunities, working alongside leading engineering experts in semiconductor technology. Qualcomm provides comprehensive benefits, including health coverage, financial planning support, and professional development programs. The company culture emphasizes innovation, collaboration, and continuous learning.
This position is perfect for experienced verification engineers passionate about GPU technology and power optimization. The role combines technical expertise with collaborative teamwork, offering the chance to contribute to cutting-edge mobile computing solutions. Qualcomm's commitment to employee development and well-being makes this an excellent opportunity for career growth in the semiconductor industry.
Responsibilities For Functional DV ( Clock/Power) Verification Staff Engineer
- Verifying Clock and power management module with design features for low power
- Understanding GPU power and clock domains with power-up/down sequences
- Own end to end DV tasks from coding Test bench and test cases
- Write assertions, debugging simulations and achieving all coverage goals
- Develop test plan to verify sequences and design components
- Collaborate with worldwide design, silicon and architecture teams
Requirements For Functional DV ( Clock/Power) Verification Staff Engineer
- Bachelor's/Master's/PhD in Computer Science, Electrical/Electronics Engineering or related field
- 5-8 years of design verification experience
- Strong System Verilog/UVM based verification skills
- Experience with assertion & coverage-based verification methodology
- Basic understanding of low power design techniques
- Experience with Synopsys NLP tool
- Strong communication skills
- Experience with scripting languages such as Perl, Python (preferred)
Benefits For Functional DV ( Clock/Power) Verification Staff Engineer
- World-class health coverage for employees and dependents
- Financial planning and future preparation programs
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship programs
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