FY25 Intern - VLSI Low Power Engineering Intern - Hod Hasharon

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Description For FY25 Intern - VLSI Low Power Engineering Intern - Hod Hasharon

Qualcomm Israel Ltd. is seeking a VLSI Low Power Engineering Intern for their Hod Hasharon location. This internship position focuses on power analysis, optimization, and verification in digital design. The ideal candidate will be a 3rd-year Electrical Engineering student with strong communication skills and English proficiency.

The role involves hands-on experience with power analysis and optimization of digital designs at both RTL and Gate levels. You'll work on developing power-intent files for multi-voltage ASIC designs and perform various power-related validations and measurements. This is an excellent opportunity to gain practical experience in low-power design techniques while working with cutting-edge technology.

Key responsibilities include performing power analysis, implementing optimization techniques, supporting power-aware verification, and conducting silicon power measurements. Knowledge of scripting languages (Python/Perl/TCL) and familiarity with Verilog/Sys-Verilog HDL languages are preferred skills that will enhance your effectiveness in this role.

At Qualcomm, you'll work alongside leading engineering and technology experts, benefiting from mentorship opportunities and continuous learning programs. The company offers comprehensive benefits including health coverage, financial planning support, and wellbeing programs. This internship provides an excellent stepping stone for a career in low-power VLSI design and optimization.

Join Qualcomm to be part of a team that's driving innovation in wireless technology and semiconductors, while developing your technical and professional skills in a supportive, inclusive environment.

Last updated a month ago

Responsibilities For FY25 Intern - VLSI Low Power Engineering Intern - Hod Hasharon

  • Performing Power analysis and power estimation of digital designs (RTL & Gate level)
  • Performing power optimizations using different techniques and different tools
  • Supporting Power Aware verification at RTL/Gate level
  • Define and develop power-intent files (like UPF) for multi-voltage ASIC designs
  • Perform low power structural validation at RTL/Gate level
  • Perform Silicon power measurements and analysis

Requirements For FY25 Intern - VLSI Low Power Engineering Intern - Hod Hasharon

Python
  • 3rd year in EE studies
  • Very Good communication skills
  • Very good verbal and written English
  • Knowledge in script writing in Python/Perl/TCL (preferred)
  • Familiarity with Verilog/Sys-Verilog HDL languages (preferred)
  • Familiarity with UNIX development environment (preferred)

Benefits For FY25 Intern - VLSI Low Power Engineering Intern - Hod Hasharon

Medical Insurance
Mental Health Assistance
Education Budget
  • Health coverage for employees and eligible dependents
  • Financial planning and security programs
  • Emotional/mental health support
  • Wellbeing programs
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

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