High-Speed PLL Digital Design Lead Engineer
Description For High-Speed PLL Digital Design Lead Engineer
Qualcomm India Private Limited is seeking a High-Speed PLL Digital Design Lead Engineer to join their hardware engineering team in Bangalore. This role focuses on front-end digital design implementation of high-speed PLL designs and requires expertise in RTL development, verification, and chip-level integration. The position demands strong technical skills in hardware engineering, particularly in areas like micro-architecture development, RTL design, and front-end flows. The ideal candidate will have 5+ years of experience and strong educational background in Computer Science or Electrical Engineering.
The role offers an opportunity to work with cutting-edge technology in wireless communications and semiconductor design. You'll be responsible for developing timing constraints, working on power-aware designs, and collaborating with cross-functional teams globally. The position requires expertise in DFT insertion, ATPG analysis, and provides exposure to both pre and post-silicon debug processes.
Qualcomm offers comprehensive benefits including world-class health coverage, financial planning assistance, and professional development opportunities. The company maintains a strong focus on work-life balance and employee wellbeing, providing various support programs for emotional and mental health. The collaborative work environment encourages innovation and professional growth through continuous learning programs and mentorship opportunities.
This is an excellent opportunity for experienced hardware engineers looking to advance their careers with a global technology leader. The role combines technical challenges with professional growth opportunities, making it ideal for those passionate about digital design and hardware engineering.
Responsibilities For High-Speed PLL Digital Design Lead Engineer
- Front-End/Digital design implementation of high speed PLL designs
- RTL development and validation for linting, clock-domain crossing, conformal low power and DFT rules
- Work with functional verification team on test-plan development and debug
- Develop timing constraints, deliver synthesized netlist to physical design team
- UPF writing, power aware equivalence checks and low power checks
- DFT insertion and ATPG analysis for optimal SAF, TDF coverage
- Provide support to SoC integration and chip level pre/post-silicon debug
Requirements For High-Speed PLL Digital Design Lead Engineer
- Bachelor's/Master's degree in Computer Science, Electrical/Electronics Engineering or related field
- 5+ years of Hardware Engineering experience
- Experience in micro-architecture development, RTL design, front-end flows
- Experience with post-silicon bring-up and debug is a plus
- Able to work with teams across the globe and possess good communication skills
Benefits For High-Speed PLL Digital Design Lead Engineer
- World-class health coverage for employees and eligible dependents
- Financial programs to help build secure future
- Emotional/mental strength and resilience support
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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