Implementation Timing / STA Design Engineer
Description For Implementation Timing / STA Design Engineer
Qualcomm's SoC Implementation Team is seeking skilled engineers to focus on timing constraints development, power analysis, STA, and timing closure for premium-tier chips. This role offers an excellent opportunity to join the Snapdragon implementation team, responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors.
Key responsibilities include:
- Developing constraints for physical power-aware synthesis
- Setting up various modes/corners and low-power multi-voltage domain crossings
- Performing signoff with static timing analysis
- Collaborating with RTL design and physical design teams
- Generating, reviewing, and validating clock domain crossing and design constraints
- Reviewing and integrating HM constraints into SoC
- Analyzing timing across modes and corners
The ideal candidate should have at least 2 years of experience and be proficient with tools such as Primetime and Fishtail/TCM. Scripting skills in Tcl, Perl, or Python are desirable.
Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design experience
- OR Master's degree in Science, Engineering, or related field and 3+ years of experience
- OR PhD in Science, Engineering, or related field and 2+ years of experience
Qualcomm offers a competitive compensation package, including an annual discretionary bonus program and opportunity for annual RSU grants. The company also provides a comprehensive benefits package designed to support employees' success at work, home, and play.
Join Qualcomm to work on cutting-edge technology and be part of a team that's shaping the future of communication and data processing.
Responsibilities For Implementation Timing / STA Design Engineer
- Develop constraints for physical power-aware synthesis
- Set up various modes/corners and low-power multi-voltage domain crossings
- Perform signoff with static timing analysis
- Collaborate with RTL design and physical design teams
- Generate, review, and validate clock domain crossing and design constraints
- Review and integrate HM constraints into SoC
- Ensure correlation between HM and SoC timing
- Analyze timing across modes and corners
- Understand concepts like path pessimism and margins
Requirements For Implementation Timing / STA Design Engineer
- Bachelor's, Master's, or PhD degree in Science, Engineering, or related field
- 2-4+ years of ASIC design, verification, validation, integration, or related work experience
- Proficiency with tools such as Primetime and Fishtail/TCM
- Experience in timing constraints development, power analysis, and STA
- Knowledge of physical power-aware synthesis
- Understanding of low-power multi-voltage domain crossings
- Ability to collaborate with RTL design and physical design teams
- Experience with clock domain crossing and design constraints
- Familiarity with HM constraints and SoC timing correlation
- Understanding of timing analysis across modes and corners
- Desirable: Scripting skills in Tcl, Perl, or Python
Benefits For Implementation Timing / STA Design Engineer
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Comprehensive health benefits
- Financial planning and wealth-building programs
- Emotional and mental wellbeing support
- Work-life balance resources
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
