LPASS DV Sr Lead Engineer

A leading technology innovator that pushes boundaries to enable next-generation experiences and drives digital transformation for a smarter, connected future.
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Senior Software Engineer
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6+ years of experience
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Description For LPASS DV Sr Lead Engineer

Qualcomm is seeking a Senior Lead Engineer for their LPASS (Low Power Audio Subsystem) Hardware team in Bangalore. This role is part of a worldwide team responsible for developing and delivering cutting-edge audio solutions that set benchmarks in the mobile computing industry. The position requires deep understanding of hardware architecture while working with the latest DV tools and technologies.

As a LPASS DV Sr Lead Engineer, you'll be responsible for owning and developing verification solutions for critical audio subsystem features. You'll work with state-of-the-art verification methodologies including formal, simulation, and emulation-based approaches. The role involves creating robust testbenches, optimizing verification processes, and ensuring silicon quality through comprehensive testing strategies.

The ideal candidate brings 1-6 years of VLSI industry experience with strong expertise in SystemVerilog, UVM, and hardware verification. You'll need excellent debugging skills using tools like Verdi, proficiency in scripting languages (Perl/Python), and knowledge of low-power architectures. This position offers the opportunity to work with leading technology experts and contribute to world-changing innovations that power Snapdragon-based computing devices.

Qualcomm offers comprehensive benefits including world-class health coverage, financial planning support, wellbeing programs, and continuous learning opportunities. Join a team that values innovation, collaboration, and professional growth while working on technologies that impact lives globally.

Last updated 13 minutes ago

Responsibilities For LPASS DV Sr Lead Engineer

  • DV ownership of one or more features in the Low power audio subsystem(LPASS) core
  • Developing a robust testbench, optimized for the specific feature/DUT
  • Explore innovative DV methodologies (formal, simulation and emulation based)
  • Ensure bug-free silicon for Tape Out
  • Continuously push quality and efficiency of test benches and process improvements

Requirements For LPASS DV Sr Lead Engineer

Python
  • Bachelor's/Master's/PhD in Computer Science, Electrical/Electronics Engineering or related field
  • 1-6 years of VLSI industry experience
  • Strong debugging and analytical skills
  • Strong knowledge of HDLs like Verilog, System Verilog
  • Proficiency in developing SV/UVM based test benches
  • Proficient in debugging RTL/TB issues using Verdi or similar tools
  • Proficient with scripting languages such as Perl and Python
  • Knowledge of UPF, low power architecture (preferred)

Benefits For LPASS DV Sr Lead Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and eligible dependents
  • Financial planning and future security programs
  • Emotional/mental health support
  • Wellbeing programs and resources
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship opportunities

Interested in this job?

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