LPASS DV Sr Lead Engineer

A leading technology innovator that pushes boundaries to enable next-generation experiences and drives digital transformation for a smarter, connected future.
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
6+ years of experience
AI · Enterprise SaaS

Description For LPASS DV Sr Lead Engineer

Qualcomm, a pioneering technology innovator, is seeking a LPASS DV Sr Lead Engineer to join their Hardware team in Bangalore. This role is part of a worldwide team responsible for developing and delivering cutting-edge Audio solutions that set industry benchmarks in mobile computing. The position requires deep understanding of hardware architecture while working with the latest DV tools and technologies.

The ideal candidate will lead verification efforts for the Low Power Audio Subsystem (LPASS), developing robust testbenches and exploring innovative methodologies across formal, simulation, and emulation-based approaches. This role offers the opportunity to work on Snapdragon-based computing devices, ensuring superior user experiences through bug-free silicon delivery.

Qualcomm offers an exceptional environment for career growth, working alongside leading engineering and technology experts. The company provides comprehensive benefits including world-class health coverage, financial planning support, and extensive professional development opportunities. Their inclusive culture encourages innovation and collaboration, making it an ideal place for those passionate about pushing technological boundaries.

The role combines technical leadership with hands-on engineering, requiring expertise in hardware verification, VLSI, and modern testing methodologies. Success in this position demands both technical excellence and the ability to work effectively with cross-functional teams to develop groundbreaking solutions.

Last updated 3 months ago

Responsibilities For LPASS DV Sr Lead Engineer

  • DV ownership of features in the Low power audio subsystem(LPASS) core
  • Developing robust testbench, optimized for specific features/DUT
  • Explore innovative DV methodologies for quality and efficiency improvements
  • Ensure bug-free silicon for Tape Out
  • Collaborate with cross-functional teams to develop solutions

Requirements For LPASS DV Sr Lead Engineer

Python
  • Bachelor's/Master's/PhD in Computer Science, Electrical/Electronics Engineering or related field
  • 1-6 years of VLSI industry experience
  • Strong debugging and analytical skills
  • Strong knowledge of HDLs like Verilog, System Verilog
  • Proficiency in developing SV/UVM based test benches
  • Proficient in debugging RTL/TB issues using Verdi or similar tools
  • Proficient with scripting languages such as Perl and Python
  • Knowledge of UPF, low power architecture (preferred)

Benefits For LPASS DV Sr Lead Engineer

Medical Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning programs
  • Emotional/mental health support
  • Wellbeing programs
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship programs

Interested in this job?

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