Physical Design Engineer - Sr Engineer

Leading technology innovator that pushes boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation.
$115,600 - $173,400
Backend
Senior Software Engineer
In-Person
3+ years of experience
Enterprise SaaS

Description For Physical Design Engineer - Sr Engineer

Qualcomm Technologies, Inc., a leading technology innovator, is seeking a Senior Physical Design Engineer to join their Digital ASIC Team. This role offers an exciting opportunity to work on cutting-edge chip design and implementation at one of the world's foremost semiconductor companies.

The position involves working with state-of-the-art tools and technologies to develop complex, high-speed, low power designs such as GPU, Camera, DDR, Modem, and Audio components. As a senior engineer, you'll be responsible for the complete Physical Design Flow, from initial conception to final product delivery.

The role requires expertise in various aspects of chip design, including floorplanning, power planning, IR drop analysis, cell placement, and timing optimization. You'll work with advanced tools like Cadence Innovus and Synopsys Fusion Compiler, while applying your knowledge of scripting languages such as Python, PERL/TCL, and Linux/Unix shell.

This position offers competitive compensation ($115,600 - $173,400) along with excellent benefits including medical insurance, 401k, annual bonuses, and RSU grants. The role is based in San Diego, California, offering the opportunity to work with some of the industry's leading experts in semiconductor design.

The ideal candidate will have 3+ years of industry experience in physical design and ASIC implementation, with a strong background in formal verification and power domain analysis. This role presents an excellent opportunity for career growth and the chance to contribute to groundbreaking technological innovations at a company that's shaping the future of mobile and wireless technology.

Last updated 2 days ago

Responsibilities For Physical Design Engineer - Sr Engineer

  • Innovate, develop, and implement chips and cores using state-of-the-art tools
  • Complete Physical Design Flow and deliveries of complex, high-speed, low power designs
  • Development of low power implementation methods
  • Floorplanning and power planning
  • IR drop analysis and cell placement
  • Multi-mode & multi-corner clock tree synthesis
  • Timing optimization and closure
  • Debugging timing violations and implementing fixes
  • Formal verification

Requirements For Physical Design Engineer - Sr Engineer

Python
Linux
  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design experience
  • Physical Design - Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
  • Timing closure experience in Synopsys PTSI
  • Formal verification experience
  • Power domain analysis experience
  • Physical verification experience
  • Deep knowledge of scripting languages including Python, PERL/TCL, Linux/Unix shell and C

Benefits For Physical Design Engineer - Sr Engineer

Medical Insurance
401k
Education Budget
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Medical Insurance
  • 401k
  • Education Budget

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