Physical Design Staff Engineer

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space.

Key Responsibilities: • Participate in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. • Create design experiments and conduct detailed PPA (Performance, Power, Area) comparison analysis to improve quality of results, tuning recipes, and setting project direction. • Collaborate closely with RTL design, Synthesis, Low Power, Thermal, Power Analysis, and Power Estimation teams to optimize PPA. • Develop Place & Route recipes for optimal PPA. • Tabulate metrics results for analysis comparison.

Required Qualifications: • 10-15 years of High Performance core Place & Route and ASIC design Implementation work experience. • Extensive experience in Place & Route with FC or Innovus is an absolute must. • Complete ASIC flow knowledge with low power, performance, and area optimization techniques. • Experience with STA using Primetime and/or Tempus. • Proficiency in constraint generation and validation. • Experience in multiple power domain implementation with complex UPF/CPF definition. • Formal verification experience (Formality/Conformal). • Perl/Tcl, Python, C++ skills. • Strong problem-solving and ASIC development/debugging skills. • Experience with CPU micro-architecture and critical path understanding. • Low power implementation techniques experience. • High-speed CPU implementation experience. • Clock Tree Implementation Techniques for High Speed Design Implementation. • Exposure to Constraint management tools and Verilog coding experience.

Education: • Required: Bachelor's in Electrical Engineering or equivalent experience. • Preferred: Master's in Electrical Engineering or equivalent experience.

This role offers an exciting opportunity to work on cutting-edge technology in a fast-paced environment, collaborating with cross-functional teams to deliver high-performance SoCs for various markets.