Senior Staff ASIC RTL Design (Turing) - Engineer
Description For Senior Staff ASIC RTL Design (Turing) - Engineer
Qualcomm, a leading technology innovator, is seeking a Senior Staff ASIC RTL Design Engineer for their Turing team. This role represents an exciting opportunity to work at the forefront of AI and ML hardware development.
The position involves leading and executing complex RTL design projects for AI/ML systems, requiring deep expertise in computer architecture and low-power design techniques. You'll be responsible for developing implementation strategies that optimize performance, power, area, and schedule (PPAS) goals for subsystems.
As a Senior Staff Engineer, you'll lead a team in RTL coding for subsystem/SOC integration, while working closely with product definition and architecture teams. Your responsibilities will include defining critical aspects of block-level design such as interfaces, clocking, transaction flow, and pipeline architecture. You'll also drive quality initiatives through Lint/CDC/FV/UPF checks and develop assertions for white-box testing coverage.
The ideal candidate brings 12+ years of experience and deep knowledge of Verilog/System Verilog, with proven expertise in high-performance design techniques and AI/ML systems. Understanding of NoC Design principles and experience with simulation tools is essential. You'll collaborate with various stakeholders, including Power and Synthesis teams, to deliver high-quality design collaterals.
Qualcomm offers a comprehensive benefits package including world-class health coverage, financial planning support, mental health resources, and continuous learning opportunities. Join us in pushing the boundaries of what's possible in AI/ML hardware design while working with some of the industry's brightest minds in a collaborative, innovative environment.
Responsibilities For Senior Staff ASIC RTL Design (Turing) - Engineer
- Interact closely with product definition and architecture team
- Develop implementation strategies for subsystem quality and PPAS goals
- Define block level design aspects including interfaces, clocking, and pipeline
- Lead RTL coding team for subsystem/SOC integration
- Drive Lint/CDC/FV/UPF checks for design quality
- Develop Assertions for white-box testing-coverage
- Work with stakeholders on collateral quality
- Deliver key design collaterals
Requirements For Senior Staff ASIC RTL Design (Turing) - Engineer
- Bachelor's degree in Computer Science/Electrical Engineering with 6+ years experience or Master's with 5+ years or PhD with 4+ years
- Understanding of low power microarchitecture techniques and AI/ML systems
- Knowledge of Computer system architecture and AI/ML designs
- Experience in high performance design techniques
- Understanding of NoC Design principles
- Knowledge of Verilog / System Verilog
- Experience with simulators and waveform debugging tools
- Knowledge of logic design principles
Benefits For Senior Staff ASIC RTL Design (Turing) - Engineer
- World-class health coverage for employees and dependents
- Financial planning and future security programs
- Mental health and emotional support resources
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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