SOC Design Verification - Principal Engineer
Description For SOC Design Verification - Principal Engineer
Qualcomm India Private Limited is seeking a Principal Engineer for SOC Design Verification to join their Hardware Engineering team in Bangalore. This role represents an exciting opportunity to work with cutting-edge semiconductor technology at one of the world's leading tech companies.
As a Principal Engineer in SOC Design Verification, you'll be responsible for managing complex verification processes for UFS/Ethernet/PCIe and high-speed IP at the System-on-Chip level. Your expertise will be crucial in ensuring the quality and reliability of Qualcomm's semiconductor products.
The ideal candidate brings 8+ years of hardware engineering experience, with deep expertise in verification methodologies and tools. You'll need strong technical skills in System Verilog, UVM, and various verification tools, combined with excellent problem-solving abilities and leadership qualities.
At Qualcomm, you'll work alongside some of the industry's brightest minds, contributing to world-changing innovations in mobile and semiconductor technology. The company offers comprehensive benefits, including world-class health coverage, financial planning support, and continuous learning opportunities.
This role offers significant growth potential and the chance to work on cutting-edge technology that impacts billions of devices worldwide. You'll be part of a collaborative team environment that values innovation, technical excellence, and professional development.
The position requires a strong background in electronics engineering, verification experience, and expertise in various protocols and tools. You'll lead verification efforts, collaborate across teams, and help drive technical excellence in SOC design verification.
Join Qualcomm to be part of a company that's shaping the future of technology while enjoying excellent career growth opportunities and comprehensive benefits. Your work will directly impact the next generation of semiconductor technology and mobile communications.
Responsibilities For SOC Design Verification - Principal Engineer
- Manage UFS/Ethernet/PCIe/high speed IP verification at SoC level
- Understand design specification and implementation
- Define verification scope and develop test plans
- Implement and analyze system Verilog assertion and coverage
- Work with verification team to analyze, develop and execute test cases
- Collaborate with architects, designers, and pre/post silicon verification teams
Requirements For SOC Design Verification - Principal Engineer
- B.E/B.Tech/M.E/M.Tech in electronics with 5+ years verification experience
- Experience with IP level or SoC level verification
- Knowledge of UFS, Ethernet and PCIe Protocol
- Understanding of processor-based SoC level verification
- Experience with verification tools (VCS, waveform analyzer)
- Expertise in UVM, C/C++, System Verilog
- Understanding of AXI-AMBA protocol variants
- Scripting knowledge (shell, Makefile, Perl)
- Strong problem solving and debugging skills
Benefits For SOC Design Verification - Principal Engineer
- World-class health coverage for employees and dependents
- Financial planning and security programs
- Mental health and emotional support resources
- Wellbeing programs
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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