Sr. Staff Design Engineer (Low Power)

A wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for mobile, networking, computing and consumer electronics markets.
$176,300 - $264,500
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
7+ years of experience
AI

Description For Sr. Staff Design Engineer (Low Power)

Qualcomm Atheros is seeking a Sr. Staff Design Engineer specializing in low power design for their wireless technology team. This role represents a unique opportunity to work with cutting-edge WiFi (802.11x) technology and SOC Design at a global leader in wireless technologies.

The position involves working on critical aspects of low power micro-architecture, power implementation, and optimization for wireless solutions. You'll be responsible for developing technical specifications, delivering detailed designs, and working through the entire ASIC development lifecycle from conception to post-silicon validation.

As a senior technical leader, you'll provide guidance to team members while working on complex challenges in power optimization and silicon design. The role requires extensive experience in ASIC design, particularly in low power architectures and ARM-based systems. You'll collaborate with cross-functional teams, including verification engineers, to ensure successful product delivery.

The compensation package is highly competitive, ranging from $176,300 to $264,500, complemented by annual bonuses, RSU grants, and comprehensive benefits. Qualcomm offers excellent career growth opportunities, working alongside industry experts in wireless technology.

This role is ideal for experienced engineers passionate about low power design and wireless technologies, offering the chance to work on innovative solutions that impact global wireless communications. The position is based in Santa Clara, California, at the heart of Silicon Valley's tech ecosystem.

Working at Qualcomm means joining a team that values innovation, collaboration, and technical excellence. The company provides extensive resources for professional development, including continuous learning programs, tuition reimbursement, and mentorship opportunities. The work environment promotes both technical growth and work-life balance through comprehensive wellness programs and support systems.

Last updated a day ago

Responsibilities For Sr. Staff Design Engineer (Low Power)

  • Develop technical specifications from Architectural and systems requirements
  • Deliver detailed low power micro-architecture and design
  • Work with verification team to develop verification plans
  • Own design through full ASIC development process
  • Responsible for silicon power measurements, Si debug and power correlation
  • Responsible for full chip debug design using ARM IPs
  • Provide supervision/guidance to other team members

Requirements For Sr. Staff Design Engineer (Low Power)

  • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design experience
  • 7+ years of working experience in ASIC Design
  • Experience in silicon bring up and debug
  • Experience on SoC micro architecture, multi-domain clocking, AMBA bus protocols
  • Experience in low power micro-architecture, Design, Power Intent/Implementation
  • Experience in ARM IP based full chip debug
  • Experience in PCIE/USB peripherals
  • Experience in CPU sub system-based design

Benefits For Sr. Staff Design Engineer (Low Power)

Medical Insurance
401k
Equity
  • Competitive annual discretionary bonus program
  • Annual RSU grants
  • Comprehensive health benefits
  • Financial planning support
  • Emotional/mental health support
  • Wellbeing programs

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