Sr.Staff SoC Lead design verification Engineer

Qualcomm Atheros is seeking a Senior Staff SoC Lead Design Verification Engineer to lead a team of ASIC design verification engineers in Santa Clara. This role offers an exciting opportunity to work at the forefront of wireless technology and connectivity solutions.

The position involves leading verification efforts for IP and Subsystems that are integrated into Qualcomm's WIFI, connectivity, and IOT devices. You'll work closely with SoC Architects, software teams, validation teams, and design teams to ensure IP meets power, performance, and area goals for Qualcomm's wireless and connectivity products.

As a technical leader, you'll be responsible for defining processes, methods, and tools for design verification of large complex IP blocks and subsystems. The role requires extensive experience in digital verification, including test automation, coverage-driven verification, and system Verilog/UVM-based verification skills.

The position offers a competitive compensation package ranging from $176,300 to $264,500, along with comprehensive benefits including medical insurance, 401k, equity grants, and annual bonuses. Qualcomm provides a collaborative environment where innovation is encouraged and technical excellence is valued.

Key responsibilities include leading Sub-System & SoC Design verification for WIFI projects, managing test bench architecture, collaborating with cross-geographical teams, and mentoring other engineers. The ideal candidate will have 8+ years of semiconductor ASIC DV experience and 2+ years of leadership experience taking projects to tape out.

This role represents an excellent opportunity for an experienced verification engineer looking to take on a leadership position at a company that's at the forefront of wireless technology innovation. You'll have the chance to work on cutting-edge projects while building and leading a team of talented engineers.